Y. Hirano

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2001 .

Threshold voltage adjustment in SOI MOSFETs by employing tantalum for gate material

T. Ohmi, H. Shimada, T. Ushiki, 1995, Proceedings of International Electron Devices Meeting.

Reliable tantalum gate fully-depleted-SOI MOSFETs with 0.15 /spl mu/m gate length by low-temperature processing below 500/spl deg/C

T. Ohmi, H. Shimada, M. Morita, 1996, International Electron Devices Meeting. Technical Digest.

Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications

Tadahiro Ohmi, T. Ushiki, Hisayuki Shimada, 1997 .

Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

Tadahiro Ohmi, Mizuho Morita, T. Ushiki, 1997 .