Yuji Kukimoto

发表

Rectification method for lookup-table type FPGA's

Masahiro Fujita, Yuji Kukimoto, 1992, ICCAD.

Static timing analysis

Karem A. Sakallah, Yuji Kukimoto, Michel Berkelaar, 2001 .

Combinational verification based on high-level functional specifications

Robert K. Brayton, Eugene Goldberg, Yuji Kukimoto, 1998, Proceedings Design, Automation and Test in Europe.

Rectification method for lookup-table type FPGA's

Masahiro Fujita, Yuji Kukimoto, M. Fujita, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Timing analysis and optimization for high-performance digital circuits

Robert K. Brayton, Yuji Kukimoto, 1998 .

VIS: A System for Verification and Synthesis

Tiziano Villa, Stephen A. Edwards, Szu-Tsung Cheng, 1996, CAV.

Hierarchical functional timing analysis

Robert K. Brayton, Yuji Kukimoto, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio

Hiroshi Nakamura, Masahiro Fujita, Hidehiko Tanaka, 1990, CAV.

A redesign technique for combinational circuits based on gate reconnections

Robert K. Brayton, Masahiro Fujita, Yuji Kukimoto, 1994, ICCAD.

Exact required time analysis via false path detection

Robert K. Brayton, Yuji Kukimoto, 1997, DAC.

Application of Boolean unification to combinational logic synthesis

Masahiro Fujita, Kuang-Chien Chen, Yuji Kukimoto, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Canonical TBDD's and Their Application to Combinational Verification

Robert K. Brayton, Yuji Kukimoto, Evguenii I. Goldberg, 1997 .

Patching Method for Lookup-Table Type FPLs

Masahiro Fujita, Yuji Kukimoto, 1992, FPL.

Refining switching window by time slots for crosstalk noise calculation

Kurt Keutzer, Pinhong Chen, Yuji Kukimoto, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Rectification Method for

Masahiro Fujita, Yuji Kukimoto, 1992 .

Approximate timing analysis of combinational circuits under the XBDO model

Robert K. Brayton, Alexander Saldanha, Wilsin Gosti, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Computing Delay with Coupling Using Timed Automata

Robert K. Brayton, Yuji Kukimoto, Serdar Tas, 1997 .

Practical design assistance at register transfer level using a data path verifier

Hiroshi Nakamura, Masahiro Fujita, Hidehiko Tanaka, 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio

Masahiro Fujita, Hidehiko Tanaka, Hiroshi Nakamura, 1990, CAV.

Refining switching window by time slots for crosstalk noise calculation

Kurt Keutzer, Pinhong Chen, Yuji Kukimoto, 2002, ICCAD 2002.

Approximate timing analysis of combinational circuits under the XBD0 model

Robert K. Brayton, Alexander Saldanha, Wilsin Gosti, 1997, ICCAD 1997.

Delay-optimal technology mapping by DAG covering

Robert K. Brayton, Prashant Sawkar, Yuji Kukimoto, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A Redesign Technique For Combinational Circuits Based On Gate Recomections

Robert K. Brayton, Masahiro Fujita, Yuji Kukimoto, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Physical Prototyping Plans for High Performance

Chin-Chi Teng, Pinhong Chen, Yuji Kukimoto, 2004 .

Timing-safe false path removal for combinational modules

Robert K. Brayton, Yuji Kukimoto, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Session details: Session 10A: Don't care optimization and boolean matching

Prabhakar Kudva, Yuji Kukimoto, 2001, ICCAD 2001.

BDD minimization by truth table permutations

Robert K. Brayton, Masahiro Fujita, Yuji Kukimoto, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

Delay Characterization of Combinational Modulesby Functional Arrival Time Analysis

Yuji Kukimoto, K. Robert, BraytonAbstractA, 1998 .

Hierarchical Timing Analysis under the XBD0 Model

Robert K. Brayton, Yuji Kukimoto, 1997 .