W. Sułek

Message Quantization Scheme for Nonbinary LDPC

W. Sułek, 2015 .

Pipeline processing in low-density parity-check codes hardware decoder

W. Sułek, 2011 .

Idle time reduction in TDMP implementation of LDPC decoder

Wojciech Sulek, W. Sułek, 2010, 2010 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering (SIBIRCON).

Energy-Efficient Raptor-like LDPC Coding Scheme Design and Implementation for IoT Communication Systems

W. Sułek, Jakub Hyla, 2023, Energies.

Hardware implementation of the LDPC decoder in the FPGA structure

Dariusz Kania, Wojciech Sulek, Mateusz Kuc, 2021 .

Low Power QC-LDPC Decoder Based on Token Ring Architecture

Dariusz Kania, Mateusz Kuc, Wojciech Sulek, 2020, Energies.

FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

Dariusz Kania, Mateusz Kuc, Wojciech Sulek, 2020, Mathematics.

On the Overflow Problem in Finite Precision Turbo Decoding Message Passing

Wojciech Sulek, W. Sułek, 2012, IEEE Transactions on Communications.

Transmission over UWB channels with OFDM system using LDPC coding

Wojciech Sulek, Grzegorz Dziwoki, Marcin Kucharczyk, 2009, Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (WILGA).

Code construction algorithm for architecture aware LDPC codes with low-error-floor

D. Kania, W. Sulek, D. Kania, 2008, 2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering.

Protograph Based Low-Density Parity-Check Codes Design With Mixed Integer Linear Programming

Wojciech Sułek, W. Sułek, 2019, IEEE Access.

Nonbinary Quasi-Regular QC-LDPC Codes Derived From Cycle Codes

Wojciech Sułek, W. Sułek, 2016, IEEE Communications Letters.

Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation

Wojciech Sulek, W. Sułek, 2016, Circuits, Systems, and Signal Processing.