Jun Lin

发表

An Efficient VLSI Architecture for

Zhongfeng Wang, Jun Lin, Jin Sha, 2010 .

APPROXIMATE BELIEF PROPAGATION DECODER FOR POLAR CODE

Weikang Qian, Jun Lin, Menghui Xu, 2017 .

A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm

Zhongfeng Wang, Jiajun Wu, Jun Lin, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA

Zhongfeng Wang, Jun Lin, Luyi Li, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

An Efficient Hardware Accelerator for Sparse Transformer Neural Networks

Zhongfeng Wang, Jun Lin, Ming-Kai Hsu, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT

Siyuan Lu, Keli Xie, Zhongfeng Wang, 2022, 2211.08842.

Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT

Siyuan Lu, Keli Xie, Zhongfeng Wang, 2022, ArXiv.

A Reconfigurable DNN Training Accelerator on FPGA

Zhongfeng Wang, Jun Lin, Jinming Lu, 2020, 2020 IEEE Workshop on Signal Processing Systems (SiPS).

Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model

Zhongfeng Wang, Jun Lin, Binjing Li, 2020, 2020 IEEE Workshop on Signal Processing Systems (SiPS).

FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Yizhi Wang, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks

Zhongfeng Wang, Yizhi Wang, Jun Lin, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Yizhi Wang, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network

Zhongfeng Wang, Wenjian Liu, Jun Lin, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Tianyi Xu, 2019, ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Methodology for Efficient Reconfigurable Architecture of Generative Neural Network

Zhongfeng Wang, Jichen Wang, Wendong Mao, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

An Optimized Architecture For Decomposed Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Fangxuan Sun, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks

Zhongfeng Wang, Jun Lin, Fangxuan Sun, 2018, 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks

Zhongfeng Wang, Jun Lin, Jinming Lu, 2020, 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training

Zhongfeng Wang, Jun Lin, Jinming Lu, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm pdf

Zhongfeng Wang, Jun Lin, Haonan Wang, 2019, ArXiv.

Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer pdf

Siyuan Lu, Meiqi Wang, Jun Lin, 2020, 2020 IEEE 33rd International System-on-Chip Conference (SOCC).

E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory

Zhongfeng Wang, Meiqi Wang, Jun Lin, 2019, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks

Zhongfeng Wang, Meiqi Wang, Li Du, 2019, 2019 IEEE International Workshop on Signal Processing Systems (SiPS).

Accelerating Recurrent Neural Networks: A Memory-Efficient Approach

Zhongfeng Wang, Jun Lin, Zhisheng Wang, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TIE: Energy-efficient Tensor Train-based Inference Engine for Deep Neural Network

Chunhua Deng, Zhongfeng Wang, Xuehai Qian, 2019, 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA).

Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning

Danyang Zhu, Siyuan Lu, Meiqi Wang, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning

Danyang Zhu, Zhongfeng Wang, Meiqi Wang, 2018, 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A lightweight face detector by integrating the convolutional neural network with the image pyramid

Jun Lin, Zhongfeng Wang, Jiaying Liu, 2020, Pattern Recognit. Lett..

Reduced complexity belief propagation decoders for polar codes

Zhiyuan Yan, Chenrong Xiong, Jun Lin, 2015, 2015 IEEE Workshop on Signal Processing Systems (SiPS).

Evaluations on Deep Neural Networks Training Using Posit Number System

Jun Lin, Zhongfeng Wang, Chao Fang, 2020, IEEE Transactions on Computers.

Optimized sorting network for successive cancellation list decoding of polar codes

Li Li, Fan Feng, Feng Han, 2017, IEICE Electron. Express.

Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes

Fakhreddine Ghaffari, David Declercq, Jun Lin, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Low-Complexity Decoder for Turbo Product Codes Based on Extended Hamming Codes

Zhongfeng Wang, Yaqi Wang, Jun Lin, 2018, 2018 IEEE 18th International Conference on Communication Technology (ICCT).

Symbol-Decision Successive Cancellation List Decoder for Polar Codes

Zhiyuan Yan, Chenrong Xiong, Jun Lin, 2015, IEEE Transactions on Signal Processing.

An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems

Zhongfeng Wang, Jun Lin, Jing Zeng, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes

Zhongfeng Wang, Jun Lin, Keyue Deng, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Information Storage Bit-Flipping Decoder for LDPC Codes

Zhongfeng Wang, Jun Lin, Hangxuan Cui, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fine-Grained Bit-Flipping Decoding for LDPC Codes

Jun Lin, Yuxing Chen, Hangxuan Cui, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

An Enhanced Offset Min-Sum decoder for 5G LDPC Codes

David Declercq, Zhongfeng Wang, Khoa LeTrung, 2019, 2019 25th Asia-Pacific Conference on Communications (APCC).

A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes

David Declercq, Zhongfeng Wang, Ghaffari Fakhreddine, 2019, 2019 19th International Symposium on Communications and Information Technologies (ISCIT).

A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes

Zhongfeng Wang, Jun Lin, Jing Tian, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes

Zhongfeng Wang, Jun Lin, Hangxuan Cui, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

An efficient post processing scheme to lower the error floor of LDPC decoders

Zhongfeng Wang, Jun Lin, Wenjie Li, 2017, 2017 IEEE 17th International Conference on Communication Technology (ICCT).

A reduced complexity decoding algorithm for NB-LDPC codes

Zhongfeng Wang, Jun Lin, Suwen Song, 2017, 2017 IEEE 17th International Conference on Communication Technology (ICCT).

Modified shuffled schedule for nonbinary low-density parity-check codes

Zhiyuan Yan, Jun Lin, Zhiyuan Yan, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes

Zhongfeng Wang, Jun Lin, Jin Sha, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An improved min-sum based column-layered decoding algorithm for LDPC codes

Zhongfeng Wang, Jun Lin, Jin Sha, 2009, 2009 IEEE Workshop on Signal Processing Systems.

Decoder Design for RS-Based LDPC Codes

Zhongfeng Wang, Jun Lin, Jin Sha, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

LDPC decoder design for IEEE 802.15 standard

Jun Lin, Zhongfeng Wang, Li Li, 2009, 2009 IEEE International Symposium on Circuits and Systems.

LDPC decoder design for high rate wireless personal area networks

Zhongfeng Wang, Jun Lin, Jin Sha, 2009, IEEE Transactions on Consumer Electronics.

Low-complexity shift-LDPC decoder for high-speed communication systems

Zhongfeng Wang, Chuan Zhang, Jun Lin, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Flexible LDPC Decoder Design for Multigigabit-per-Second Applications

Zhongfeng Wang, Chuan Zhang, Jun Lin, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

Zhongfeng Wang, Jun Lin, Jin Sha, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

Training Deep Neural Networks Using Posit Number System

Siyuan Lu, Zhongfeng Wang, Li Du, 2019, 2019 32nd IEEE International System-on-Chip Conference (SOCC).

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation

Jun Lin, Zhe Liu, Zhongfeng Wang, 2022, IEEE Transactions on Computers.

Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography

Jun Lin, Zhongfeng Wang, Jing Tian, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks

Jun Lin, Zhongfeng Wang, Xiaoru Xie, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator

Jun Lin, Zhongfeng Wang, Wenjian Liu, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Efficient Hardware Architectures for Deep Convolutional Neural Network

Zhongfeng Wang, Jun Lin, Jichen Wang, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading

Jun Lin, Siyuan Lu, Shuang Liang, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning

Zhongfeng Wang, Yizhi Wang, Jun Lin, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Symbol-based successive cancellation list decoder for polar codes

Zhiyuan Yan, Chenrong Xiong, Jun Lin, 2014, 2014 IEEE Workshop on Signal Processing Systems (SiPS).

LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion

Jun Lin, Siyuan Lu, Zhongfeng Wang, 2020, 2020 International Joint Conference on Neural Networks (IJCNN).

An Efficient FPGA Accelerator for Point Cloud

Zhongfeng Wang, Jun Lin, W. Mao, 2022, 2022 IEEE 35th International System-on-Chip Conference (SOCC).

Efficient Reconfigurable Hardware Core for Convolutional Neural Networks

Zhongfeng Wang, Yi Xie, Bo Yuan, 2018, 2018 52nd Asilomar Conference on Signals, Systems, and Computers.

In-Memory Computing: The Next-Generation AI Computing Paradigm

Zhongfeng Wang, Li Du, Jun Lin, 2020, ACM Great Lakes Symposium on VLSI.