Massimo Violante

发表

Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”

D. Bortolato, M. Ceschia, Massimo Violante, 2003 .

Anexperimental analysi sofhardening techniques forSRAM-based FPGAs

Massimo Violante, Luca Sterpone, S. Rezgui, 2005 .

A Fault Injection Environment for SoPC's Embedded Microprocessors

Massimo Violante, Luca Sterpone, Marta Portela-Garcia, 2006, Latin American Test Workshop - LATW.

An hybrid architecture to detect transient faults in microprocessors: An experimental validation

Massimo Violante, Salvatore Campagna, M. Violante, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An integrated approach for increasing the soft-error detection capabilities in SoCs processors

Paolo Bernardi, Massimo Violante, Maurizio Rebaudengo, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

Coping with Obsolescence of Processor Cores in Critical Applications

Massimo Violante, Francesco Abate, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Early reliability evaluation of a biomédical system

Massimo Violante, Matteo Sonza Reorda, Paolo Rech, 2014, 2014 9th International Design and Test Symposium (IDT).

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

Niccolò Battezzati, Massimo Violante, Chiara Sandionigi, 2010, 2010 15th IEEE European Test Symposium.

Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparative study and experimental results

Massimo Violante, Maurizio Rebaudengo, Raoul Velazco, 2001 .

Efficient analysis of single event transients

Massimo Violante, Matteo Sonza Reorda, 2004, J. Syst. Archit..

Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2003, J. Electron. Test..

System-Level Considerations

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

Hardening the software with respect to transient errors: a method and experimental results

Massimo Violante, Maurizio Rebaudengo, Raoul Velazco, 2000 .

Reconfigurable Field Programmable Gate Arrays: Failure Modes and Analysis

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

Luigi Carro, Massimo Violante, Matteo Sonza Reorda, 2007, J. Electron. Test..

A new framework for the automatic insertion of mitigation structures in circuits netlists

Niccolò Battezzati, Massimo Violante, Davide Serrone, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

A Novel Method for Online Detection of Faults Affecting Execution-Time in Multicore-Based Systems

Massimo Violante, Stefano Esposito, Marco Sozzi, 2017, ACM Trans. Embed. Comput. Syst..

A P1500-compatible programmable BIST approach for the test of embedded flash memories

Paolo Bernardi, Massimo Violante, Maurizio Rebaudengo, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Final Report on Project Results

Petru Eles, Zebo Peng, Massimo Violante, 2000 .

An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard

Massimo Violante, Matteo Sonza Reorda, Peter Sarson, 2017, 2017 18th IEEE Latin American Test Symposium (LATS).

Online hardening of programs against SEUs and SETs

Luigi Carro, Massimo Violante, Matteo Sonza Reorda, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Simulation-based analysis of SEU effects in SRAM-based FPGAs

D. Bortolato, M. Ceschia, Massimo Violante, 2004 .

Reconfigurable Field Programmable Gate Arrays: Hardening Solutions

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders

Salvatore Pontarelli, Adelio Salsano, Massimo Violante, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Mitigating Soft Errors in Processors Cores Embedded in System-on Programmable-Chips

Massimo Violante, Stefano Esposito, 2016 .

A programmable BIST approach for the diagnosis of embedded memory cores

Massimo Violante, Paolo Bernardi, Maurizio Rebaudengo, 2003 .

Online time interference detection in mixed-criticality applications on multicore architectures using performance counters

Massimo Violante, Stefano Esposito, Marco Sozzi, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor

Massimo Violante, Matteo Sonza Reorda, Julio Perez Acle, 2011, 2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS).

A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices

Massimo Violante, Luca Sterpone, Niccolo Battezzati, 2008, WREFT '08.

Putting Mitigation Techniques at Work

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

Development and Assessment of Pressure-Based and Model-Based Techniques for the MFB50 Control of a Euro VI 3.0L Diesel Engine

Christian Maier, Massimo Violante, Ezio Spessa, 2017 .

A new software-based technique for low-cost fault-tolerant application

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2003, Annual Reliability and Maintainability Symposium, 2003..

Guest Editorial

Massimo Violante, Prashant D. Joshi, 2013, J. Electron. Test..

Simulation-based analysis of SEU effects in SRAM-based FPGAs

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2004, IEEE Transactions on Nuclear Science.

Fault list compaction through static timing analysis for efficient fault injection experiments

Massimo Violante, Matteo Sonza Reorda, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

An in-vehicle infotainment software architecture based on google android

Marco Torchiano, Massimo Violante, Gianpaolo Macario, 2009, 2009 IEEE International Symposium on Industrial Embedded Systems.

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017

Massimo Violante, Jie Han, Intel L. Dilillo, 2017, DFT.

A new decompression system for the configuration process of SRAM-based FPGAS

Massimo Violante, Luca Sterpone, M. Violante, 2007, GLSVLSI '07.

New techniques for accelerating fault injection in VHDL descriptions

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

On the Consolidation of Mixed Criticalities Applications on Multicore Architectures

Massimo Violante, Stefano Esposito, 2017, J. Electron. Test..

Evaluating system dependability in a co-design framework

Luciano Lavagno, Massimo Violante, Maurizio Rebaudengo, 2000, DATE '00.

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects

Görschwin Fey, Massimo Violante, Matteo Sonza Reorda, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications

Massimo Violante, Luca Sterpone, 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

Fault Injection-based Reliability Evaluation of SoPCs

Massimo Violante, Matteo Sonza Reorda, Luis Entrena, 2006, Eleventh IEEE European Test Symposium (ETS'06).

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications

Jaan Raik, Massimo Violante, Siavoosh Payandeh Azad, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Innovative practices on quality levels of A/MS devices

Wim Dobbelaere, Jeff Rearick, Massimo Violante, 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

Embedded Low Power Controller for Autonomous Landing of Small UAVs using Neural Network

Massimo Violante, Ahmad Din, Basilio Bona, 2012 .

Dependability evaluation of transient fault effects in reconfigurable compute fabric devices

Massimo Violante, Luca Sterpone, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Embedded virtualization techniques for automotive infotainment applications

Massimo Violante, Salvatore Campagna, Gianpaolo Macario, 2014 .

Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits

Massimo Violante, Matteo Sonza Reorda, 2003, FPL.

An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications

Marco Torchiano, Massimo Violante, Maurizio Rebaudengo, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems

Massimo Violante, Serhiy Avramenko, 2019, J. Electron. Test..

Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications

Massimo Violante, Salvatore Campagna, Moazzam Hussain, 2010, DFT.

On-line analysis and perturbation of CAN networks

Massimo Violante, Matteo Sonza Reorda, 2004 .

Boosting software fault injection for dependability analysis of real-time embedded applications

Massimo Violante, Gianpiero Cabodi, Marco Murciano, 2010, TECS.

New techniques for efficiently assessing reliability of SOCs

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2003, Microelectron. J..

Commercial Off-the-Shelf Components in Space Applications

Massimo Violante, Stefano Esposito, 2016 .

A source-to-source compiler for generating dependable software

Marco Torchiano, Massimo Violante, Maurizio Rebaudengo, 2001, Proceedings First IEEE International Workshop on Source Code Analysis and Manipulation.

A design flow for protecting FPGA-based systems against single event upsets

Massimo Violante, Luca Sterpone, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

System-level Test and Validation of Hardware/Software Systems

Zebo Peng, Massimo Violante, Matteo Sonza Reorda, 2005 .

FPGA-based fault injection for microprocessor systems

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2001, Proceedings 10th Asian Test Symposium.

Accurate single-event-transient analysis via zero-delay logic simulation

Massimo Violante, 2003 .

Evaluation of error effects on a biomedical system

Massimo Violante, Enea Bagalini, H. Hakobyan, 2015, 2015 IEEE East-West Design & Test Symposium (EWDTS).

Real-Time Validation of Fault-Tolerant Mixed-Criticality Systems

Massimo Violante, Stefano Esposito, Jacopo Sini, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Report on benchmark identification and planning of experiments to be performed

Zebo Peng, Massimo Violante, Matteo Sonza Reorda, 2002 .

Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs

Alessandro Paccagnella, Massimo Violante, Luca Sterpone, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Software-Implemented Hardware Fault Tolerance

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2010 .

Pandora I-IP: an HW/SW approach to Control Flow Checking

Fabian Vargas, Massimo Violante, Paolo Bernardi, 2005 .

A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips

Ricardo Reis, Massimo Violante, Matteo Sonza Reorda, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

A novel approach to improve the social acceptance of autonomous driving vehicles by recognizing the emotions of passengers

Massimo Violante, Bartolomeo Montrucchio, Antonio Costantino Marceddu, 2021, International Conference on Machine Vision.

An Automatic Approach to Perform FMEDA Safety Assessment on Hardware Designs

Massimo Violante, Jacopo Sini, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Fault-Injection Techniques for Dependability Analysis: An Overview

Massimo Violante, M. Violante, 2018, Radiation Effects in Semiconductors.

Automatic Generation ofTestSetsforSBST ofMicroprocessor IPCores

Giovanni Squillero, Massimo Violante, E. Sanchez, 2005 .

Automatic Detection and Prediction of the Transition Between the Behavioural States of a Subject Through a Wearable CPS

Eric Armengaud, Massimo Violante, Luciano Garramone, 2020 .

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Cecilia Metra, Marco Ottavi, Salvatore Pontarelli, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Accurate and efficient analysis of single event transients in VLSI circuits

Massimo Violante, Matteo Sonza Reorda, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

Fabian Vargas, Massimo Violante, Maurizio Rebaudengo, 2004 .

Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

Dependable MPSoC-Based Mixed-Criticality Systems for Space Applications

Massimo Violante, Stefano Esposito, 2018, 2018 5th IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace).

An RT-level concurrent error detection technique for data dominated systems

Massimo Violante, Matteo Sonza Reorda, Olga Goloubeva, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms

Görschwin Fey, Massimo Violante, Matteo Sonza Reorda, 2017, J. Electron. Test..

Early, accurate dependability analysis of CAN-based networked systems

Massimo Violante, Matteo Sonza Reorda, Julio Pérez Acle, 2006, IEEE Design & Test of Computers.

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs

Massimo Violante, Fernanda Gusmão de Lima Kastensmidt, Luca Sterpone, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Efficient estimation of SEU effects in SRAM-based FPGAs

Massimo Violante, Matteo Sonza Reorda, Luca Sterpone, 2005, 11th IEEE International On-Line Testing Symposium.

System safety through automatic high-level code transformations: an experimental evaluation

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

On Reducing the Peak Power Consumption of Test Sequences

Massimo Violante, Maurizio Rebaudengo, Fulvio Corno, 1999 .

A Low-Cost Solution for Deploying Processor Cores in Harsh Environments

Ricardo Reis, Massimo Violante, Matteo Sonza Reorda, 2011, IEEE Transactions on Industrial Electronics.

Low power BIST via non-linear hybrid cellular automata

Giovanni Squillero, Massimo Violante, Maurizio Rebaudengo, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Hardware-in-the-loop-based dependability analysis of automotive systems

Massimo Violante, Matteo Sonza Reorda, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips

Massimo Violante, Luca Sterpone, Francesco Abate, 2008 .

A new approach to cope with single event upsets in processor-based systems

Massimo Violante, Matteo Sonza Reorda, Massimiliano Schillaci, 2006 .

A Light-Weight Fault Tolerance Framework for Space Computing using COTS Components

Massimo Violante, Salvatore Campagna, Moazzam Hussain, 2011, ARCS Workshops.

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs

Massimo Violante, Luca Sterpone, 2007, 12th IEEE European Test Symposium (ETS'07).

A simulation-based methodology for aiding advanced driver assistance systems hazard analysis and risk assessment

Massimo Violante, J. Sini, 2020 .

Software Techniques for Dependable Computer-based Systems

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2004 .

Reconfigurable Field Programmable Gate Arrays: Basic Concepts

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

High-level and hierarchical test sequence generation

Zebo Peng, Massimo Violante, Matteo Sonza Reorda, 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

Optimization of Self Checking FIR filters by means of Fault Injection Analysis

Salvatore Pontarelli, Adelio Salsano, Massimo Violante, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Dependability analysis of CAN networks: an emulation-based approach

Massimo Violante, Matteo Sonza Reorda, J. Pérez, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2001, FPL.

RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC

Massimo Violante, Stefano Esposito, Serhiy Avramenko, 2018, 2018 IEEE 19th Latin-American Test Symposium (LATS).

A genetic algorithm-based system for generating test programs for microprocessor IP cores

Giovanni Squillero, Massimo Violante, Matteo Sonza Reorda, 2000, Proceedings 12th IEEE Internationals Conference on Tools with Artificial Intelligence. ICTAI 2000.

An adaptively reconfigurable computing framework for intelligent Robotics

Massimo Violante, Ahmad Din, Basilio Bona, 2011, 2011 IEEE/ASME International Conference on Advanced Intelligent Mechatronics (AIM).

Automatic generation of validation stimuli for application-specific processors

Massimo Violante, Matteo Sonza Reorda, Olga Goloubeva, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Combined software and hardware techniques for the design of reliable IP processors

Massimo Violante, Maurizio Rebaudengo, Donatella Sciuto, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Deterministic network on chip for deploying real time applications on many-core processors

Massimo Violante, Stefano Esposito, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis

Jaan Raik, Massimo Violante, Siavoosh Payandeh Azad, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A hierarchical approach for designing dependable systems

Salvatore Venticinque, Giuliana Franceschinis, Nicola Mazzocca, 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

New evolutionary techniques for test-program generation for complex microprocessor cores

Giovanni Squillero, Massimo Violante, Matteo Sonza Reorda, 2005, GECCO '05.

Exploiting FPGA for accelerating fault injection experiments

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2001, Proceedings Seventh International On-Line Testing Workshop.

Soft errors in Flash-based FPGAs: Analysis methodologies and first results

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Exploiting symbolic techniques for partial scan flip flop selection

Paolo Prinetto, Massimo Violante, Matteo Sonza Reorda, 1998, Proceedings Design, Automation and Test in Europe.

Message from the Symposium Chairs

Massimo Violante, Fabio Salice, Prashant D. Joshi, 2005, SRDS.

Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs

Niccolò Battezzati, Massimo Violante, Michel Briet, 2009, 2009 15th IEEE International On-Line Testing Symposium.

Validating the dependability of embedded systems through fault injection by means of loadable kernel modules

Massimo Violante, Marco Murciano, 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

A multi-level approach to the dependability analysis of networked systems based on the CAN protocol

Massimo Violante, Matteo Sonza Reorda, Fulvio Corno, 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

Prediction of Power Requirements for High-Speed Circuits

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2000, EvoWorkshops.

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2002, J. Electron. Test..

Behavioral-level test vector generation for system-on-chip designs

Luciano Lavagno, Massimo Violante, Maurizio Rebaudengo, 2000, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs

Ricardo Reis, Massimo Violante, Matteo Sonza Reorda, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Soft-error detection using control flow assertions

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Exploiting circuit emulation for fast hardness evaluation

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2001 .

Multilevel Simulation Methodology for FMECA Study Applied to a Complex Cyber-Physical System

Massimo Violante, Matteo Sonza Reorda, Radu Bojoi, 2020 .

On-line detection of control-flow errors in SoCs by means of an infrastructure IP core

Fabian Vargas, Paolo Bernardi, Massimo Violante, 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

ETS 2013 Best Paper

Massimo Violante, 2013, ETS 2013.

Cerberus I-IP: an HW/SW approach to Control Flow Checking

Fabian Vargas, Massimo Violante, Paolo Bernardi, 2004 .

Automatic Emotion Recognition for the Calibration of Autonomous Driving Functions

Massimo Violante, Antonio Costantino Marceddu, Jacopo Sini, 2020, Electronics.

A new functional fault model for FPGA application-oriented testing

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

ISO26262-Compliant Development of a High Dependable Automotive Powertrain Item

Massimo Violante, J. Sini, Riccardo Dessi, 2020 .

Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems

Giovanni Squillero, Massimo Violante, Ernesto Sánchez, 2004, EvoWorkshops.

Multiple errors produced by single upsets in FPGA configuration memory: a possible solution

Massimo Violante, Matteo Sonza Reorda, Luca Sterpone, 2005, European Test Symposium (ETS'05).

A new hybrid fault detection technique for systems-on-a-chip

Fabian Vargas, Paolo Bernardi, Massimo Violante, 2006, IEEE Transactions on Computers.

Massively Extended Modular Monitoring and a Second Life for Upper Stages

Massimo Violante, Matteo Sonza Reorda, Stefan Söderholm, 2018 .

Advanced technologies for transient faults detection and compensation

Massimo Violante, Matteo Sonza Reorda, Luca Sterpone, 2011 .

FAULT TOLERANT DIGITAL SYSTEMS DESIGN 01LHUIU (Presentation of the course)

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2003 .

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

D. Bortolato, Paolo Bernardi, Alessandro Paccagnella, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Automotive embedded software architecture in the multi-core age

Massimo Violante, Paolo Gai, 2016, 2016 21th IEEE European Test Symposium (ETS).

An Infrastructure IP for Soft Error Detection

Fabian Vargas, Massimo Violante, Maurizio Rebaudengo, 2004 .

Analysis of SEU effects in a pipelined processor

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

Early evaluation of bus interconnects dependability for system-on-chip designs

Massimo Violante, Matteo Sonza Reorda, Marcello Lajolo, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Validation of the dependability of CAN-based networked systems

Massimo Violante, Matteo Sonza Reorda, Fulvio Corno, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

High-level test generation for hardware testing and software validation

Massimo Violante, Matteo Sonza Reorda, Olga Goloubeva, 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

On the test of microprocessor IP cores

Giovanni Squillero, Massimo Violante, Matteo Sonza Reorda, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Automatic test bench generation for simulation-based validation

Luciano Lavagno, Massimo Violante, Maurizio Rebaudengo, 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).

Test Pattern Generation Under Low Power Constraints

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 1999, EvoWorkshops.

Passengers' Emotions Recognition to Improve Social Acceptance of Autonomous Driving Vehicles

Massimo Violante, Antonio Costantino Marceddu, Jacopo Sini, 2017, IIH-MSP.

On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs

Niccolò Battezzati, Alessandro Paccagnella, Massimo Violante, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Test techniques for Advanced Processors

Massimo Violante, M. Sonza Reorda, M. Reorda, 2005 .

Recovery scheme for hardening system on programmable chips

Massimo Violante, Matteo Sonza Reorda, Ricardo Reis, 2009, 2009 10th Latin American Test Workshop.

Hardening FPGA-based Systems Against SEUs: A New Design Methodology

Massimo Violante, Luca Sterpone, 2006, J. Comput..

Exploiting programmable bist for the diagnosis of embedded memory cores

Paolo Bernardi, Massimo Violante, Maurizio Rebaudengo, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

Luigi Carro, Massimo Violante, Matteo Sonza Reorda, 2008, J. Electron. Test..

A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices

Gian Carlo Cardarilli, Salvatore Pontarelli, Adelio Salsano, 2007 .

Real-time validation of mixed-criticality applications

Massimo Violante, Stefano Esposito, Jacopo Sini, 2018, 2018 IEEE 19th Latin-American Test Symposium (LATS).

ALPS: a peak power estimation tool for sequential circuits

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Exploiting logic simulation to improve simulation-based sequential ATPG

Paolo Prinetto, Massimo Violante, Maurizio Rebaudengo, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Embedded Low Power Controller for Autonomous Landing of UAV Using Artificial Neural Network

Massimo Violante, Basilio Bona, Ahmad Din, 2012, 2012 10th International Conference on Frontiers of Information Technology.

Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables

Görschwin Fey, Massimo Violante, Matteo Sonza Reorda, 2016, 2016 17th Latin-American Test Symposium (LATS).

Report on Dissemination Plan

Petru Eles, Zebo Peng, Massimo Violante, 2002 .

Designing Autonomous Race Car Models for Learning Advanced Topics in Hard Real-Time System

Massimo Violante, Enea Bagalini, 2015, Int. J. Robotics Appl. Technol..

Software-level soft-error mitigation techniques

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2011 .

An automatic approach to integration testing for critical automotive software

Massimo Violante, Jacopo Sini, A. Mugoni, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Early Power Estimation for System-on-Chip Designs

Luciano Lavagno, Massimo Violante, Matteo Sonza Reorda, 2000, PATMOS.

A New Approach to Software-Implemented Fault Tolerance

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2004, J. Electron. Test..

Rice Coding-Based Lite Compression Algorithm with Controlled Error for Sensor Data

Massimo Violante, Stefano Esposito, Serhiy Avramenko, 2018, 2018 5th IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace).

On-line analysis and perturbation of CAN networks

Massimo Violante, Matteo Sonza Reorda, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

A Hybrid Fault Injection Methodology for Real Time Systems

Alfredo Benso, Paolo Prinetto, Raimund Ubar, 1998 .

Multi-level Fault Effects Evaluation

Massimo Violante, Maurizio Rebaudengo, M. Sonza Reorda, 2007 .

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2014 .

Reprogrammable FPGAs for Mission-Critical Applications

Niccolò Battezzati, Massimo Violante, Luca Sterpone, 2011 .

Test Generation: A Heuristic Approach

Massimo Violante, M. Sonza Reorda, O. Goloubeva, 2005 .

Speeding-Up Fault Injection Campaigns in VHDL Models

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2000, SAFECOMP.

Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs

Massimo Violante, Luca Sterpone, Miguel A. Aguirre, 2011, IEEE Transactions on Industrial Electronics.

A new approach to compress the configuration information of programmable devices

Guido Masera, Massimo Violante, Luca Sterpone, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Massimo Violante, Luca Sterpone, M. Violante, 2006, IEEE Transactions on Computers.

Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard

Massimo Violante, Matteo Sonza Reorda, Peter Sarson, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

A fully-automated flow for ITAR-free rad-hard Atmel FPGAs

Massimo Violante, Nikos Andrikos, David Merodio Codinachs, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2002 .

On the evaluation of SEU sensitiveness in SRAM-based FPGAs

Paolo Bernardi, Massimo Violante, Matteo Sonza Reorda, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

A new hardware architecture for performing the gridding of DNA microarray images

Massimo Violante, Luca Sterpone, M. Violante, 2007, GLSVLSI '07.

Computer-Aided Design of Multi-Agent Cyber-Physical Systems

Massimo Violante, Jacopo Sini, R. Dessi, 2018, 2018 IEEE 23rd International Conference on Emerging Technologies and Factory Automation (ETFA).

SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information

Heinrich Theodor Vierhaus, Paolo Prinetto, Massimo Violante, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the consolidation of mixed criticalities applications on multicore architectures

Massimo Violante, Stefano Esposito, Serhiy Avramenko, 2016, 2016 17th Latin-American Test Symposium (LATS).

System-level test bench generation in a co-design framework

Luciano Lavagno, Massimo Violante, Maurizio Rebaudengo, 2000, Proceedings IEEE European Test Workshop.

Software and Hardware Techniques for SEU Detection in IP Processors

Massimo Violante, Donatella Sciuto, Luca Sterpone, 2008, J. Electron. Test..

A low-cost solution for developing reliable Linux-based space computers for on-board data handling

Massimo Violante, M. L. Esposti, 2009, 2009 15th IEEE International On-Line Testing Symposium.

Detailed comparison of dependability analyses performed at RT and gate levels

Régis Leveugle, Massimo Violante, Matteo Sonza Reorda, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Soft-error detection through software fault-tolerance techniques

Marco Torchiano, Massimo Violante, Maurizio Rebaudengo, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Low Power BIST via Hybrid Cellular Automata

Giovanni Squillero, Massimo Violante, Maurizio Rebaudengo, 2000 .

Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Automatic Generation of Test Sets for SBST of Microprocessor IP Cores

Giovanni Squillero, Massimo Violante, Matteo Sonza Reorda, 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

System-level architecture for mixed criticality applications on MPSoC: A space application

Massimo Violante, Stefano Esposito, M. Violante, 2017, 2017 IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace).

Optimal vector selection for low power BIST

Massimo Violante, Maurizio Rebaudengo, Matteo Sonza Reorda, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Analyzing SEU effects is SRAM-based FPGAsb

D. Bortolato, Paolo Bernardi, Alessandro Paccagnella, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications

Paolo Bernardi, Massimo Violante, Matteo Sonza Reorda, 2006, Seventh International Workshop on Microprocessor Test and Verification (MTV'06).

A multi-level approach to the dependability analysis of CAN networks for automotive applications

Massimo Violante, Fulvio Corno, Matteo Sonza Reorda, 2004 .

Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems

Massimo Violante, Stefano Esposito, Serhiy Avramenko, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

A local analysis of the genotype-fitness mapping in hardware optimization problems

Giovanni Squillero, Massimo Violante, Ernesto Sánchez, 2004, Proceedings of the 2004 Congress on Evolutionary Computation (IEEE Cat. No.04TH8753).

A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories

Dan Alexandrescu, Enrico Costenaro, Massimo Violante, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

A framework to support the design of COTS-based reliable space computers for on-board data handling

Massimo Violante, Salvatore Campagna, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

An Hybrid Architecture for consolidating mixed criticality applications on multicore systems

Massimo Violante, Stefano Esposito, Marco Sozzi, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

Fabian Vargas, Massimo Violante, Maurizio Rebaudengo, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Design and rapid prototyping of a closed-loop control strategy of the injected mass for the reduction of CO2, combustion noise and pollutant emissions in diesel engines

Massimo Violante, Alessandro Ferrari, C. Novara, 2018, Applied Energy.

Power Consumption Versus Configuration SEUs in Xilinx Virtex-5 FPGAs

Massimo Violante, Luca Sterpone, Vincenzo Izzo, 2013, IEEE Transactions on Nuclear Science.