A. Ray

A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology

Jonghae Kim, M. Sherony, J. Plouchart, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A 0.18 /spl mu/m high-performance logic technology

S. Greco, M. Hargrove, X. Chen, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Application of an SOI

S. Narasimha, N. Lustig, S. Kosonocky, 2003 .

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A high-performance 0.08 /spl mu/m CMOS

E. Nowak, A. Ray, P. Agnello, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

Liang-Hung Lu, M. Sherony, Jonghae Kim, 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.

A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS

Jean-Olivier Plouchart, Jonghae Kim, Yue Tan, 2003, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003.