D.A. Antoniadis

Design methodology for minimizing hysteretic V/sub T/-variation in partially-depleted SOI CMOS

A. Wei, D.A. Antoniadis, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

S. Narendra, V. De, A.P. Chandrakasan, 2004, IEEE Journal of Solid-State Circuits.

Measurement of minimum-geometry MOS transistor capacitances

D.A. Antoniadis, J.J. Paulos, D. Antoniadis, 1985, IEEE Transactions on Electron Devices.

Fabrication of fully self-aligned joint-gate CMOS structures

D.A. Antoniadis, A. L. Robinson, A.L. Robinson, 1985, IEEE Transactions on Electron Devices.

Limitations of quasi-static capacitance models for the MOS transistor

D.A. Antoniadis, J.J. Paulos, 1983, IEEE Electron Device Letters.

A RF power LDMOS device on SOI

D.A. Antoniadis, J.G. Fiorenza, J.A. Del Alamo, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).