Jeffrey P. Gambino

Gate manufacturing process for the dram-range and logic components on the same chip

Ramachandra Divakaruni, Gary Stormville Bronner, Richard A. Conti, 2001 .

A 0.6 /spl mu/m/sup 2/ 256 Mb trench DRAM cell with self-aligned BuriEd STrap (BEST)

Jack A. Mandelman, John K. DeBrosse, A. Nitayama, 1993, Proceedings of IEEE International Electron Devices Meeting.

The move to 300-mm wafers : A prime time to consider reclaim

Florian Schnabel, Jeffrey P. Gambino, Lynne M. Gignac, 1998 .

Dual damascene aluminum for 1-Gbit DRAMs

Florian Schnabel, Jeffrey P. Gambino, Lynne M. Gignac, 1998 .

An overview of through-silicon-via technology and manufacturing challenges

John U. Knickerbocker, Jeffrey P. Gambino, Shawn A. Adderly, 2015 .

Reliability challenges for advanced copper interconnects: Electromigration and time-dependent dielectric breakdown (TDDB)

Fen Chen, Jeffrey P. Gambino, Timothy D. Sullivan, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Self-aligned metal capping layers for copper interconnects using electroless plating

Chee Lip Gan, Jeffrey P. Gambino, M. Hernandez, 2006 .

Dielectric degradation mechanism for copper interconnects capped with CoWP

Chee Lip Gan, Jeffrey P. Gambino, J. Gambino, 2008 .