Chi-Chao Wang

Workload-adaptive process tuning strategy for power-efficient multi-core processors

Yu Cao, Nam Sung Kim, Hamid Reza Ghasemi, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

The potential of Fe-FET for robust design under variations: A compact modeling study

Yu Cao, Yun Ye, Chi-Chao Wang, 2012, Microelectron. J..

Modeling of layout-dependent stress effect in CMOS design

Min Chen, Yu Cao, Wei Zhao, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Leakage reduction through optimization of regular layout parameters

Yu Cao, Chi-Chao Wang, Anupama R. Subramaniam, 2012, Microelectron. J..

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Xia Li, Yu Cao, Wei Zhao, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation

Yu Cao, Sani R. Nassif, Asha Balijepalli, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design rule optimization of regular layout for leakage reduction in nanoscale design

Yu Cao, Chi-Chao Wang, Anupama R. Subramaniam, 2008, 2008 Asia and South Pacific Design Automation Conference.

Simulation of random telegraph Noise with 2-stage equivalent circuit

Yu Cao, Yun Ye, Chi-Chao Wang, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Compact modeling of Fe-FET and implications on variation-insensitive design

Yu Cao, Yun Ye, Chi-Chao Wang, 2010, 2010 International Conference on Simulation of Semiconductor Processes and Devices.

Compact modeling of stress effects in scaled CMOS

Yu Cao, Chi-Chao Wang, Wei Zhao, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Intrinsic Variability and Reliability in Nano-CMOS

Yu Cao, Yun Ye, Chi-Chao Wang, 2011 .