S. Utsugi

发表

A 12 ns 8 MB DRAM secondary cache for a 64 b microprocessor

I. Naritake, M. Togo, T. Sugibayashi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 1 Gb DRAM for file applications

I. Naritake, T. Murotani, T. Sugibayashi, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.