M. Dehan

发表

Impact of multi-gate device architectures on digital and analog circuits and its implications on System-On-Chip technologies

P. Wambacq, A. Mercha, G. Van der Plas, 2013, 2013 IEEE International Electron Devices Meeting.

VCO design for 60 GHz applications using differential shielded inductors in 0.13 μm CMOS

J. Borremans, M. Kuijk, M. Dehan, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

A 60-GHz LNA and a 92-GHz Low-Power Distributed Amplifier in CMOS with Above-IC

G. Carchon, W. de Raedt, B. Parvais, 2008, 2008 European Microwave Integrated Circuit Conference.

Tapped integrated inductors: Modelling and Application in Multi-Band RF Circuits

P. Wambacq, S. Decoutere, J. Borremans, 2008, 2008 European Microwave Integrated Circuit Conference.

Group IV channels for 7nm FinFETs: Performance for SoCs power and speed metrics

A. Mercha, D. Verkest, P. Raghavan, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

P. Wambacq, B. Parvais, A. Mercha, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Advanced Process Modules for (sub-) 45nm Analog/RF CMOS - Technology Description and Modeling Challenges

B. Parvais, A. Mercha, S. Decoutere, 2006, 2006 European Microwave Integrated Circuits Conference.

Low-cost feedback-enabled LNAs in 45nm CMOS

P. Wambacq, A. Mercha, J. Borremans, 2009, 2009 Proceedings of ESSCIRC.

Perspectives of (sub-) 32nm CMOS for Analog/RF and mm-wave Applications

B. Parvais, G. Groeseneken, W. Sansen, 2008, 2008 European Microwave Integrated Circuit Conference.

T-diodes - a novel plug-and-play wideband RF circuit ESD protection methodology

P. Wambacq, G. Groeseneken, J. Borremans, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Analysis of the FinFET parasitics for improved RF performances

B. Parvais, A. Mercha, S. Decoutere, 2007, 2007 IEEE International SOI Conference.

Suitability of FinFET technology for low-power mixed-signal applications

P. Wambacq, B. Parvais, R. Rooyackers, 2006, 2006 IEEE International Conference on IC Design and Technology.

Stochastic Matching Properties of FinFETs

B. Parvais, A. Mercha, S. Decoutere, 2006, IEEE Electron Device Letters.

A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS

G. Groeseneken, M. Okushima, J. Borremans, 2009, 2009 31st EOS/ESD Symposium.

Perspective of RF design in future planar and FinFET CMOS

P. Wambacq, B. Parvais, A. Mercha, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

B. Parvais, S. Van Elshocht, A. Brand, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

A low-cost 90nm RF-CMOS platform for record RF circuit performance

P. Soussan, P. Wambacq, A. Mercha, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Velocity and Mobility Investigation in 1-nm-EOT HfSiON on Si (110) and (100)—Does the Dielectric Quality Matter?

S. Severi, L. Pantisano, G. Groeseneken, 2009, IEEE Transactions on Electron Devices.

Characterization, modeling, and optimization of FinFET MOS varactors

B. Parvais, A. Mercha, S. Decoutere, 2007, 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

Lateral versus vertical gate-all-around FETs for beyond 7nm technologies

A. Mercha, D. Verkest, N. Collaert, 2014, 72nd Device Research Conference.

Alternative Architectures of SOI MOSFET for Improving DC and Microwave Characteristics

M. Dehan, D. Vanhoenacker, J.-P. Raskin, 2001, 2001 31st European Microwave Conference.

Ion-implantation-based low-cost Hk/MG process for CMOS low-power application

R. Degraeve, C. Ortolland, W. Vandervorst, 2010, 2010 Symposium on VLSI Technology.

Low temperature technology options for integrated high density capacitors

P. Soussan, E. Beyne, L. Goux, 2006, 56th Electronic Components and Technology Conference 2006.

Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance

A. Mercha, G. Van der Plas, D. Verkest, 2013, 2013 Symposium on VLSI Circuits.

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

F. Danneville, G. Dambrine, S. Lepilliet, 2003, IEEE Electron Device Letters.

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

H. Bender, G. Eneman, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

A. Mercha, S. Decoutere, N. Collaert, 2009, IEEE Electron Device Letters.