Weitao Pan

发表

AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation

Weina Wang, Zhiliang Qiu, Ya Gao, 2019, J. Circuits Syst. Comput..

Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

Liu Huan, Zhiliang Qiu, Weitao Pan, 2020 .

The Design and Implementation of IEEE 1588v2 Clock Synchronization System by Generating Hardware Timestamps in MAC Layer

Can Chen, Dong Zhang, Meng Dong, 2018, 2018 International Conference on Computer, Information and Telecommunication Systems (CITS).

A novel baseband digital signal processor IC for HINOC

Chun Yang, Hongbin Li, Shi Zhang, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

High-Performance and Range-Supported Packet Classification Algorithm for Network Security Systems in SDN

Jing Jiang, Huan Liu, Ling Zheng, 2020, 2020 IEEE International Conference on Communications Workshops (ICC Workshops).

Analysis of a Shared-Private Buffer Management Scheme for Shared Memory Switches

Ling Zheng, Dong Zhang, Zhiliang Qiu, 2018, 2018 International Conference on Computer, Information and Telecommunication Systems (CITS).

Improved analytical model for performance evaluation of crosspoint-queued switch under uniform traffic

Ling Zheng, Weitao Pan, Ya Gao, 2017, IET Networks.

Analyzing the Impact of Redundant Paths on Multistage Switch Performance

Ling Zheng, Weitao Pan, Ya Gao, 2017, ChinaCom.

Low-Cost and Programmable CRC Implementation Based on FPGA

Zhiliang Qiu, Ling Zheng, Huan Liu, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches

Weitao Pan, Ling Zheng, Ya Gao, 2020, Int. J. Commun. Syst..

Research on Model of Five-level Scheduling Based on SDN

Ling Zheng, Dong Zhang, Lili Gao, 2018, 2018 International Conference on Computer, Information and Telecommunication Systems (CITS).

Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers

Ling Zheng, Zhiliang Qiu, Zhiyi Zhang, 2018, Journal of Communications and Networks.

The High Speed Packet Classification Supporting Multi - Field for Flow Tables in OpenFlow

Ling Zheng, Weina Wang, Zhiliang Qiu, 2018, 2018 International Conference on Computer, Information and Telecommunication Systems (CITS).

Dual-Plane Switch Architecture for Time-Triggered Ethernet

Hui Jin, Hongbin Zhang, Zhiliang Qiu, 2020, ACM Great Lakes Symposium on VLSI.

The size optimize of DCVSPG logic

Yue Hao, Peijun Ma, Weitao Pan, 2009, 2009 IEEE 8th International Conference on ASIC.

A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers

Ling Zheng, Zhiliang Qiu, Weitao Pan, 2018, ChinaCom.

Dual priority congestion aware shared-resource Network-on-Chip architecture

Huaxi Gu, Peijun Ma, Jiangyi Shi, 2016, IEICE Electron. Express.

The design of HIMAC coprocessor based on HINOC 2.0

Chun Yang, Shi Zhang, Cheng Zhang, 2014, 2014 12th International Conference on Signal Processing (ICSP).

Low-Cost and Programmable CRC Implementation based on FPGA

Jun Li, Liu Huan, Zhiliang Qiu, 2020 .

Analysis and Implementation of a QoS Optimization Method for Access Networks

Ling Zheng, Zhiliang Qiu, Zhiyi Zhang, 2018, IEICE Trans. Commun..

Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal

Jiangyi Shi, Peijun Ma, Weitao Pan, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric

Weitao Pan, Ling Zheng, Ya Gao, 2021, Comput. Networks.

Design of HIMAC Coprocessor for HINOC3.0

Zhiliang Qiu, Weitao Pan, Jun Li, 2021, 2021 IEEE 6th International Conference on Computer and Communication Systems (ICCCS).

GGTS: FPGA-Based General Ground Test System for Space-Borne Equipment

Zhiliang Qiu, Weitao Pan, Jialu Mang, 2021, 2021 IEEE 6th International Conference on Computer and Communication Systems (ICCCS).

Design and Implementation of AS6802 Clock Synchronization System in TTE thernet

Zhiliang Qiu, Weitao Pan, Min Wu, 2021, 2021 IEEE 6th International Conference on Computer and Communication Systems (ICCCS).