Y.H. Chan

A 2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 /spl mu/m CMOS bulk technology

R.V. Joshi, S.P. Kowalczyk, Y.H. Chan, 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

A 8Kb domino read SRAM with hit logic and parity checker

Y.H. Chan, A.R. Pelella, A.D. Tuminaro, 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

A 2 ns access, 500 MHz 288 Kb SRAM macro

U. Bakhru, Y.H. Chan, W.V. Huott, 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

609 MHz G5 S/399 microprocessor

Y.H. Chan, E. Schwarz, W. Huott, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

High performance SRAMs in 1.5 V, 0.18 /spl mu/m partially depleted SOI technology

R.V. Joshi, S.P. Kowalczyk, Y.H. Chan, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 400 MHz S/390 microprocessor

Ching-Te Chuang, K.L. Shepard, P.J. Restle, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

760 MHz G6 S/390 microprocessor exploiting multiple Vt and copper interconnects

J. Rawlins, R. Dwyer, Y.H. Chan, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Diffusion-Weighted MR Imaging: Diagnosing Atypical or Malignant Meningiomas and Detecting Tumor Dedifferentiation

Y.H. Chan, C. Lim, W. Ng, 2008, American Journal of Neuroradiology.