H. Ishiuchi

发表

A 0.6 /spl mu/m/sup 2/ 256 Mb trench DRAM cell with self-aligned BuriEd STrap (BEST)

Jack A. Mandelman, John K. DeBrosse, A. Nitayama, 1993, Proceedings of IEEE International Electron Devices Meeting.

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

H. Mizuno, T. Morooka, K. Ohuchi, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

FinFET: the prospective multi-gate device for future SoC applications

H. Ishiuchi, N. Aoki, S. Inaba, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

New embedded DRAM technology using self-aligned salicide block (SSB) process for 0.18 /spl mu/m SOC (system on a chip)

T. Sakurai, H. Naruse, J. Kumagai, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

An experimental 4-Mbit CMOS DRAM

T. Ohsawa, T. Furuyama, T. Tanaka, 1986 .

Submicron CMOS technologies for four mega bit dynamic RAM

M. Ishikawa, O. Ozawa, H. Ishiuchi, 1985, 1985 International Electron Devices Meeting.

A new soft error mechanism of dynamic memory with grounded cell plate

H. Ishiuchi, N. Sekiguchi, Y. Okada, 1984, 1984 International Electron Devices Meeting.

An experimental 4Mb CMOS DRAM

T. Furuyama, T. Tanaka, Takashi Ohsawa, 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

MOSFET hot-carrier reliability improvement by forward-body bias

Chenming Hu, H. Ishiuchi, S. Balasubramanian, 2006, IEEE Electron Device Letters.

MOSFET design for forward body biasing scheme

Chenming Hu, H. Ishiuchi, A. Hokazono, 2006, IEEE Electron Device Letters.

A highly manufacturable high density embedded SRAM technology for 90 nm CMOS

H. Ishiuchi, K. Ishimaru, I. Kawasaki, 2002, Digest. International Electron Devices Meeting,.

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

A novel 0.15 /spl mu/m CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions

H. Koike, Y. Akasaka, K. Nakajima, 1996, International Electron Devices Meeting. Technical Digest.

Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

H. Ishiuchi, T.-J.K. Liu, K. Ishimaru, 2008, IEEE Transactions on Electron Devices.

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, 2005 IEEE International SOI Conference Proceedings.

Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

N. Nagashima, K. Ohuchi, H. Ishiuchi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

An embedded DRAM technology on SOI/bulk hybrid substrate formed with SEG process for high-end SOC application

Y. Katsumata, H. Ishiuchi, H. Oyamatsu, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Impact of Hf concentration on performance and reliability for HfSiON-CMOSFET

H. Ishiuchi, K. Ishimaru, M. Takayanagi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

High power heterojunction GaAs switch IC with P-1 dB of more than 38 dBm for GSM application

H. Ishiuchi, N. Ohbata, K. Onda, 1998, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 20th Annual. Technical Digest 1998 (Cat. No.98CH36260).

Design guideline of HfSiON gate dielectrics for 65 nm CMOS generation

H. Ishiuchi, K. Ishimaru, M. Takayanagi, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Issues and optimization of millisecond anneal process for 45 nm node and beyond

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

Y. Toyoshima, K. Ohuchi, H. Ishiuchi, 2004, IEEE Transactions on Electron Devices.

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Ultra-thin chip with permalloy film for high performance MS/RF CMOS

T. Ohguro, H. Ishiuchi, K. Ishimaru, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

Y. Toyoshima, K. Ohuchi, H. Yoshimura, 2002, Digest. International Electron Devices Meeting,.

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Y. Matsumoto, O. Ozawa, H. Ishiuchi, 1985, IEEE Transactions on Electron Devices.