J. Figueras

发表

Quiescent current estimation for current testing

L. Balado, J. Figueras, J.A. Rubio, 1992, [1992] Proceedings The European Conference on Design Automation.

LEAP: An accurate defect-free I/sub DDQ/ estimator

J. Figueras, A. Ferre, 2000, Proceedings IEEE European Test Workshop.

Current versus Voltage Testing of Bridging Defects in a Dual Port Memory Cell

J. Figueras, R. Rodriguez-Montanes, A. Rubio, 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

Some experiments in test pattern generation for FPGA-implemented combinational circuits

Y. Zorian, J. M. Portal, M. Renovell, 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).

Signal integrity loss in bus lines due to open shielding defects

J. Figueras, V. Champac, V. Avendano, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

2009 EDAA PhD Forum at DATE

Jan Reineke, Nikil Dutt, Peter Marwedel, 2009 .

Current vs. logic testability of bridges in scan chains

J. Figueras, R. Rodriguez-Montanes, A. Rubio, 1993, Proceedings ETC 93 Third European Test Conference.

Characterization of leakage power in CMOS technologies

J. Figueras, A. Ferre, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Evaluation of a Transport Protocol for its Implementation in Distributed Multimicrocomputer Control Systems

J. Figueras, A. Alabau, 1982 .

Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study

Y. Zorian, M. Renovell, J.M. Portal, 1999, European Test Workshop 1999 (Cat. No.PR00390).

Bridging Faults in CMOS: Possibilities of Current Testing

J. Figueras, J.A. Rubio, R. Rodriguez, 1990, ESSCIRC '90: Sixteenth European Solid-State Circuits Conference.

Testing the configurable interconnect/logic interface of SRAM-based FPGA's

Y. Zorian, M. Renovell, J. Figueras, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Defective Behaviour of an 8T SRAM Cell with Open Defects

P. Prinetto, R. Rodriguez-Montanes, J. Figueras, 2010, 2010 Second International Conference on Advances in System Testing and Validation Lifecycle.

Compact BIC sensor for I/sub ddq/ testing of CMOS circuits

C. Martinez, J. Figueras, E. Lupon, 1993 .

IDDQ Detectable Bridges in Combinational CMOS Circuits

J. Figueras, E. Isern, 1997 .

Estimation of the defective I/sub DDQ/ caused by shorts in deep-submicron CMOS ICs

R. Rodriguez-Montanes, J. Figueras, 1998, Proceedings Design, Automation and Test in Europe.

Electrical and topological characterization of interconnect open defects

R. Rodriguez-Montanes, J. Figueras, 2005, Proceedings. 2005 IEEE International Workshop on Current and Defect Based Testing, 2005. DBT 2005..

CMOS leakage power at cell level

L. Balado, J. Figueras, A. Ferre, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..