Toshinori Sato

发表

A Simulation Study of Energy-Efficient Microprocessors Using Canary FFs

佐藤寿倫, Toshinori Sato, 2007 .

Possibilities to miss predicting timing errors in canary flip-flops

Hiroto Yasuura, Toshinori Sato, Takanori Hayashida, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Design of Hardware/Software Co-Design Environment Using SpecC-Based Tools

Toshinori Sato, Koichiro Tanaka, Yuhei Hayashi, 2003 .

Correlation-based critical path predictors for low power microprocessors

Toshinori Sato, Itsujiro Arita, Akihiro Chiyonobu, 2003, Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003.

A. static and dynamic energy reduction technique for I-cache and BTB in embedded processors

Toshinori Sato, Hidenori Sato, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

ALU Cascading for Improving Performance Yield

Shingo Watanabe, Masanori Hashimoto, 佐藤寿倫, 2008 .

Exploiting Instruction Redundancy for Transient Fault Tolerance

Toshinori Sato, 2003 .

A Simple Mechanism for Collapsing Instructions under Timing Speculation

Toshinori Sato, 2008, IEICE Trans. Electron..

An energy-efficient clustered superscalar processor : Lower-power LSI and lower-power IP

Toshinori Sato, Akihiro Chiyonobu, 2005 .

Evaluating the Impact of Fault Recovery on Superscalar Processor Performance

Toshinori Sato, Akihiro Chiyonobu, 2006, 2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06).

Improving Energy Efficiency via Timing Fault Tolerance

Toshinori Sato, Itsujiro Arita, 2001 .

Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2019, ACM Great Lakes Symposium on VLSI.

ALU Cascading for Improving Timing Yield

Masanori Hashimoto, 佐藤寿倫, Toshinori Sato, 2008 .

A Low-Power Yet High-Speed Configurable Adder for Approximate Computing

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Hybridizing Instruction-Level Parallelism and Serialism

Toshinori Sato, 2006 .

A Fault-Tolerance Mechanism for Microprocessors Utilizing Instruction Redundancy

Toshinori Sato, Itsujiro Arita, 2002 .

A Replacement Strategy for Canary Flip-Flops

Hiroto Yasuura, Toshinori Sato, Yuji Kunitake, 2010, 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing.

Critical Issues Regarding A Variation Resilient Flip-Flop

佐藤寿倫, Toshinori Sato, Yuji Kunitake, 2007 .

Tolerating Transient Faults through an Instruction Reissue Mechanism

Toshinori Sato, Itsujiro Arita, 2001, ISCA PDCS.

An Energy-Efficient MultiCore Processor Exploiting Speculative TLP

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2006 .

Cascading ALU Operations for Improving Timing Yield (in japanese)'', IPSJ Transactions on Advanced Computing Systems

Shingo Watanabe, Masanori Hashimoto, 佐藤寿倫, 2008 .

Introduction

Kenji Kise, Toshinori Sato, Hironori Nakajo, 2007, CARN.

Improving timing error tolerance without impact on chip area and power consumption

Toshinori Sato, Takanori Hayashida, Ken Yano, 2013, International Symposium on Quality Electronic Design (ISQED).

Data Dependence Path Reductio with Tunneling Load Instructions

Toshinori Sato, 1997, ISHPC.

Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism

Toshinori Sato, Hidenori Sato, Akihiro Chiyonobu, 2007, Int. J. Comput. Their Appl..

A static and dynamic energy reduction technique for I-cache and BTB in embedded processors

Toshinori Sato, Hidenori Sato, 2004 .

Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Instruction Scheduling for Variation-Originated Variable Latencies

Shingo Watanabe, Toshinori Sato, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Typical Case Oriented Design Approach by Timing Error Prediction to Tolerate Process Variability

Toshinori Sato, Ken Yano, Toshinori Sato, 2015 .

Importance of Single-Core Performance in the Multicore Era

Toshinori Sato, Takanori Hayashida, Hideki Mori, 2012, ACSC.

Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations

Toshinori Sato, Tomoaki Ukezono, 2020, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Exploiting Input Variations for Energy Reduction

Toshinori Sato, Yuji Kunitake, 2007, PATMOS.

Evaluating low-cost fault-tolerance mechanism for microprocessors on multimedia applications

Toshinori Sato, Itsujiro Arita, Toshinori Sato, 2001, Proceedings 2001 Pacific Rim International Symposium on Dependable Computing.

Design of Multi-Functional Memory Based on FPGAs for DSPs

Toshinori Sato, Koichiro Tanaka, Yuhei Hayashi, 2003 .

Multiple Clustered Core Processors

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2006 .

Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse

Toshinori Sato, Itsujiro Arita, 2001, Euro-Par.

A trace-level value predictor for Contrail processors

Toshinori Sato, Itsujiro Arita, Takenori Koushiro, 2003, CARN.

Low-Cost Value Predictors Using Frequent Value Locality

Toshinori Sato, Itsujiro Arita, 2002, ISHPC.

Challenges in Evaluations for a Typical-Case Design Methodology

Toshinori Sato, Koichiro Tanaka, Yuji Kunitake, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Web 3Dと時空間データベースを援用した地下空間開発支援システムの設計とその実装;Web 3Dと時空間データベースを援用した地下空間開発支援システムの設計とその実装;Development of Support System for Large-Scale Underground Structures Using Web 3d Technology and RDBMS

Toshinori Sato, Hiroshi Yamachi, Hiroya Matsui, 2015 .

Table size reduction for data value predictors by exploiting narrow width values

Toshinori Sato, Itsujiro Arita, Toshinori Sato, 2000, ICS '00.

300MHz design methodology of VU for emotion synthesis

Yukio Endo, Toshinori Sato, Hiroaki Murakami, 2000, ASP-DAC.

A leakage-energy-reduction technique for cache memories in embedded processors

Toshinori Sato, Akihiro Chiyonobu, Seiichiri Fujii, 2006, J. Embed. Comput..

A Metric for the Dependability-Performance Trade-off and its Application to a Multcore Processor

佐藤寿倫, Toshinori Sato, 舟木敏正, 2008 .

Resolving Load Data Dependency Using Tunneling-Load Technique

Toshinori Sato, 1998 .

Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI

Hiroto Yasuura, Toshinori Sato, Yuji Kunitake, 2011, IEICE Trans. Electron..

Evaluating trace cache on moderate-scale processors

Toshinori Sato, 2000 .

Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation

Toshinori Sato, Asami Tanino, 2003, CAINE.

A Selective replacement method for timing-error-predicting flip-flops

Hiroto Yasuura, Toshinori Sato, Takanori Hayashida, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

Toshinori Sato, Yuji Kunitake, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A proposal of a reliability metric for dependable LSIs

Hiroto Yasuura, Toshinori Sato, 寛人安浦, 2012 .

Evaluating the impact of reissued instructions on data speculative processor performance

Toshinori Sato, 2002, Microprocess. Microsystems.

Reducing Energy Consumption via Low-Cost Value Prediction

Toshinori Sato, Itsujiro Arita, 2002, PATMOS.

Multicore Power Management Utilizing Error-Predicting Flip-flop

Toshinori Sato, Takahito Yoshiki, Takanori Hayashida, 2011, 2011 International Conference on Complex, Intelligent, and Software Intensive Systems.

Profiling with Helper Threads

Toshinori Sato, Takamasa Tokunaga, 2005, Parallel and Distributed Computing and Networks.

Ultra Low Power (ULP) Challenge in System Architecture Level : New architectures for 45-nm, 32-nm era

佐藤寿倫, Toshinori Sato, トシノリサトウ, 2007 .

A Microprocessor Architecture Utilizing Histories of Dynamic Sequences Saved in Distributed Memories

Toshinori Sato, 1998 .

A low-power high-speed accuracy-controllable approximate multiplier design

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

A Simulation Study of Combining Load Value and Address Predictors

Toshinori Sato, 1999, Int. J. High Speed Comput..

Simplifying instruction issue logic in superscalar processors

Toshinori Sato, Itsujiro Arita, 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.

Uncriticality-Directed Low-Power Instruction Scheduling

Shingo Watanabe, Toshinori Sato, Shingo Watanabe, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

A Proposal of Critical Path Predictors for Low Power Processor Architecture

Toshinori Sato, Itsujiro Arita, Akihiro Chiyonobu, 2002 .

Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism

Toshinori Sato, 2000, J. Syst. Archit..

A Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion

Toshinori Sato, Akio Kodama, 2004 .

HDL Design of ALU based on Constructive Timing Violation Technique and its Evaluation

Toshinori Sato, Itsujiro Arita, Asami Tanino, 2003 .

In search of efficient reliable processor design

Toshinori Sato, Itsujiro Arita, Toshinori Sato, 2001, International Conference on Parallel Processing, 2001..

Leakage energy reduction in register renaming

Toshinori Sato, Masaharu Goto, 2004, 24th International Conference on Distributed Computing Systems Workshops, 2004. Proceedings..

A Selective replacement method for timing-error-predicting flip-flops

Hiroto Yasuura, Toshinori Sato, Takanori Hayashida, 2011 .

A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors

Toshinori Sato, 2003 .

Non-uniform Set-Associative Caches for Power-Aware Embedded Processors

Toshinori Sato, Seiichiro Fujii, 2004, EUC.

An Energy-Efficient Scalable Instruction Window

Shingo Watanabe, 佐藤寿倫, Toshinori Sato, 2006 .

Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction

Toshinori Sato, Akihito Sakanaka, 2003, PATMOS.

Power-Performance Trade-Off of a Dependable Multicore Processor

Toshinori Sato, Toshimasa Funaki, 2007, 13th Pacific Rim International Symposium on Dependable Computing (PRDC 2007).

Formulating MITF for a Multicore Processor with SEU Tolerance

Toshinori Sato, Toshimasa Funaki, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Experiments on a space data communication protocol using the Japanese domestic communications satellite-3 (CS-3)

Kazuhiko Yamamoto, Toshinori Sato, Shigeo Yamada, 1991 .

Low Power Cache Memories Prioritizing Data

佐藤寿倫, Toshinori Sato, 藤井誠一郎, 2007 .

Constructive timing violation for improving energy efficiency

Toshinori Sato, 2001 .

Evaluating Influence of Compiler Optimizations on Data Speculation

Toshinori Sato, Kiichi Sugitani, Akihiko Hamano, 2002, J. Inf. Sci. Eng..

Partial resolution in data value predictors

Toshinori Sato, Itsujiro Arita, Toshinori Sato, 2000, Proceedings 2000 International Conference on Parallel Processing.

The potential in energy efficiency of a speculative chip-multiprocessor

Toshinori Sato, Yuu Tanaka, Takenori Koushiro, 2004, SPAA '04.

Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture

Toshinori Sato, Akihiro Chiyonobu, 2004, ISICT.

A case for exploiting complex arithmetic circuits towards performance yield enhancement

Masanori Hashimoto, Shingo Watanabe, Toshinori Sato, 2009, 2009 10th International Symposium on Quality Electronic Design.

Profile-Based Selection of Load Value and Address Predictors

Toshinori Sato, 1999, ISHPC.

Exploiting Instruction Criticality on Variation Resilient Microarchitecture Utilizing Instruction Cascading

Shingo Watanabe, Toshinori Sato, 渡辺慎吾, 2007 .

Transient Faults Tolerance Mechanism for Microprocessors

Toshinori Sato, Itsujiro Arita, Toshinori Sato, 2001 .

Comprehensive evaluation of an instruction reissue mechanism

Toshinori Sato, Itsujiro Arita, Toshinori Sato, 2000, Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000.

An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Energy-efficient instruction scheduling utilizing cache miss information

Toshinori Sato, Akihiro Chiyonobu, 2006, SIGARCH Comput. Archit. News.

The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization

Toshiyuki Yamamoto, Toshinori Sato, Itsujiro Arita, 2002, PDPTA.

Improving Critical Path Identification Accuracy

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2006 .

Performance Evaluation of a Processing Element for an On-Chip Multiprocessor (Special Issue on Super Chip for Intelligent Integrated Systems)

Toshinori Sato, Hiroyuki Takano, Masafumi Takahashi, 1994 .

Exploiting Configurability for Correct Sign Calculation in an Approximate Adder

Toshinori Sato, Tomoaki Ukezono, 2018, 2018 International SoC Design Conference (ISOCC).

Folding Active List for High Performance and Low Power

Toshinori Sato, Yuichiro Imaizumi, 2005, ISHPC.

A field-customizable and runtime-adaptable microarchitecture

Toshinori Sato, Daisuke Morishita, 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

A Multi-Performance Processor for Low Power Embedded Applications

Hiroto Yasuura, 佐藤寿倫, Toshinori Sato, 2006 .

Dynamic Instruction Scheduling for Variable-latency Arithmetic Units in Dependable Processors

Shingo Watanabe, 佐藤寿倫, Toshinori Sato, 2008 .

A simulation study of pipelining and decoupling a dynamic instruction scheduling mechanism

Toshinori Sato, 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

Power-Performance Trade-Off of a Dependable Multicore Processor

Toshinori Sato, Toshimasa Funaki, 2007 .

Cascading ALU Operations for Improving Timing Yield

Shingo Watanabe, Masanori Hashimoto, Toshinori Sato, 2008 .

Signal probability control for relieving NBTI in SRAM cells

Hiroto Yasuura, Toshinori Sato, Yuji Kunitake, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Uncriticality-directed scheduling for tackling variation and power challenges

Shingo Watanabe, Toshinori Sato, 2009, 2009 10th International Symposium on Quality Electronic Design.

History Directed Processor Architecture

Toshinori Sato, 1999 .

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications

Tadayuki Matsumura, Toshinori Sato, Tohru Ishihara, 2008, 2008 Symposium on Application Specific Processors.

Hiding Data Cache Latency with Load Address prediction

Toshinori Sato, Seigo Suzuki, Hiroshige Fujii, 1996 .

A low-power configurable adder for approximate applications

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Physical Register Access Analysis for Temperature-Aware Architecture

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2006 .

An Energy-Efficient Clustered Superscalar Processor(Digital, Low-Power LSI and Low-Power IP)

Toshinori Sato, Akihiro Chiyonobu, 2005 .

A Low-Power Instruction Issue Queue for Microprocessors

Shingo Watanabe, Toshinori Sato, Akihiro Chiyonobu, 2008, IEICE Trans. Electron..

Approximate Adder Generation for Image Processing Using Convolutional Neural Network

Toshinori Sato, Tomoaki Ukezono, Ryuta Ishida, 2018, 2018 International SoC Design Conference (ISOCC).

A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing

Masahiro Inoue, Toshinori Sato, Hiroyuki Baba, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Exploiting Trivial Computation in Dependable Processors

Toshinori Sato, Toshinori Sato, 2005, CATA.

A leakage-energy-reduction technique for highly-associative caches in embedded systems

Toshinori Sato, Akihito Sakanaka, Seiichirou Fujii, 2004, SIGARCH Comput. Archit. News.

Analysis of SER Improvement by Radiation Hardened Latches

Toshinori Sato, Takanori Hayashida, Ken Yano, 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

Indirect Tag Search Mechanism for Instruction Window Energy Reduction

Shingo Watanabe, Toshinori Sato, Akihiro Chiyonobu, 2007, 7th IEEE International Conference on Computer and Information Technology (CIT 2007).

Power and performance fitting in nanometer design

Toshinori Sato, Itsujiro Arita, Akihiro Chiyonobu, 2002, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.

Formulating Dependability-Performance Trade-off for Multiple Clustered-Core Processors

佐藤寿倫, Toshinori Sato, 舟木敏正, 2007 .

Dependability-Performance Trade-off on Multiple Clustered Core Processors

佐藤寿倫, Toshinori Sato, 舟木敏正, 2007 .

A Dependability Selection Method for Multicore Processors Considering Power-performance Trade-off

佐藤寿倫, Toshinori Sato, 舟木敏正, 2008 .

Combining variable latency pipeline with instruction reuse for execution latency reduction

Toshinori Sato, Itsujiro Arita, 2003, Systems and Computers in Japan.

Potential of Constructive Timing-Violation

Toshinori Sato, Itsujiro Arita, 2002 .

Influence of Compiler Optimizations on Value Prediction

Toshinori Sato, Itsujiro Arita, Kiichi Sugitani, 2001, HPCN Europe.

Foreword: Special section on hardware and software technologies on advanced microprocessors

Shorin Kyo, Hiroyuki Tomiyama, Toshinori Sato, 2009 .

A Preliminary Evaluation of Timing-Speculative Instruction Collapsing

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2006 .

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment

Hiroto Yasuura, Toshinori Sato, Yuji Kunitake, 2009, IEICE Trans. Electron..

An Accuracy-Configurable Adder for Low-Power Applications

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2020, IEICE Trans. Electron..

Exploiting instruction redundancy for transient fault tolerance [microprocessor applications]

Toshinori Sato, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Design and Analysis of Approximate Multipliers with a Tree Compressor

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Development of a C-Based Co-Design Environment for an FPGA/CPU Platform

Toshinori Sato, Koichiro Tanaka, Itsujiro Arita, 2004 .

Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors

Toshinori Sato, Hidenori Sato, Akihiro Chiyonobu, 2006, PATMOS.

Data dependence speculation using data address prediction and its enhancement with instruction reissue

Toshinori Sato, Toshinori Sato, 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

Instruction Scheduling for Variation-Originated Variable Latencies

Shingo Watanabe, Toshinori Sato, 2008, ISQED 2008.

Guidelines for mitigating NBTI degradation in on-chip memories

Hiroto Yasuura, Toshinori Sato, Takanori Hayashida, 2012, 2012 International Symposium on Communications and Information Technologies (ISCIT).

An Energy-Efficient Clustered Superscalar Processor

Toshinori Sato, Akihiro Chiyonobu, 2005, IEICE Trans. Electron..

Topic 4: High-Performance Architecture and Compilers

Nectarios Koziris, Avi Mendelson, Toshinori Sato, 2012, Euro-Par.

Vector Unit Architecture for Emotion Synthesis

Masaaki Oka, Yukio Endo, Toshinori Sato, 2000, IEEE Micro.

Architecture Challenge on SoC Design with Unreliable Transistors

Toshinori Sato, 2007 .

Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure

Toshinori Sato, 1999, Euro-Par.

An Adaptive Multi-Performance Processor and its Evaluation

佐藤寿倫, Toshinori Sato, 国武勇次, 2008 .

Speculative resolution of ambiguous memory aliasing

Toshinori Sato, T. Sato, 1997, Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems.

Evaluating the Critical Path Predictors Using Critical Path Detection Criteria

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2006 .

Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor

Toshinori Sato, Tongxin Yang, Tomoaki Ukezono, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Impact of Wire-delay on On-chip Cache Hierarchies in MultiCore Processors

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2007 .

Building an Architectural-level Simulator for Evaluating Timing-speculative Processors with Considering Circuit Delay

佐藤寿倫, Toshinori Sato, 昭宏千代延, 2006 .

Dynamically reducing overestimated design margin of MultiCores

Toshinori Sato, Takanori Hayashida, Ken Yano, 2012, 2012 International Conference on High Performance Computing & Simulation (HPCS).

Dependability, power, and performance trade-off on a multicore processor

Toshinori Sato, Toshimasa Funaki, 2008, 2008 Asia and South Pacific Design Automation Conference.

The KIT COSMOS Processor: Introducing CONDOR

Toshinori Sato, Itsujiro Arita, Toshinori Sato, 2000, PDPTA.