Janusz Rajski

发表

On the diagnostic resolution of signature analysis

Janusz Rajski, Jerzy Tyszer, Babak Salimi, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Innovative practices session 11C: Advanced scan methodologies [3 presentations]

Nilanjan Mukherjee, Janusz Rajski, 2015, VTS.

An algorithmic branch and bound method for PLA test pattern generation

Janusz Rajski, Markus Robinson, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Arithmetic built-in self-test for DSP cores

Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits

Janusz Rajski, Stephen Pateras, 1991 .

Delay-fault diagnosis using timing information

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power Aware Embedded Test

Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, 2011, 2011 Asian Test Symposium.

Silicon Evaluation of Static Alternative Fault Models

Janusz Rajski, Martin Keim, Chris Schuermyer, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Arithmetic Built-In Self-Test for Embedded Systems

Janusz Rajski, Jerzy Tyszer, 1997 .

A fast sequential learning technique for real circuits with application to enhancing ATPG performance

Janusz Rajski, Aiman H. El-Maleh, Mark Kassab, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Accumulator-Based Compaction of Test Responses

Janusz Rajski, Jerzy Tyszer, J. Rajski, 1993, IEEE Trans. Computers.

Cellular automata-based test pattern generators with phase shifters

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On the generation of compact test sets

Chen Wang, Janusz Rajski, Amit Kumar, 2013, 2013 IEEE International Test Conference (ITC).

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Embedded deterministic test points for compact cell-aware tests

Nilanjan Mukherjee, Friedrich Hapke, Janusz Rajski, 2015, 2015 IEEE International Test Conference (ITC).

The dynamic reduction of fault simulation

Janusz Rajski, Fadi Maamari, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testing of telecommunications hardware [Guest Editorial]

Janusz Rajski, Jerzy Tyszer, 1999, IEEE Commun. Mag..

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures

Nilanjan Mukherjee, Yan Dong, Janusz Rajski, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Arithmetic built-in self-test for digital signal processing architectures

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays

Janusz Rajski, Ajai Jain, J. Rajski, 1989 .

Test Power Reduction by Blocking Scan Cell Outputs

Janusz Rajski, Xijiang Lin, 2008, 2008 17th Asian Test Symposium.

High-frequency, at-speed scan testing

Janusz Rajski, Nagesh Tamarapalli, Bruce Swanson, 2003, IEEE Design & Test of Computers.

Test Sequence-Optimized BIST for Automotive Applications

Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, 2020, 2020 IEEE European Test Symposium (ETS).

Design of random pattern testable floating point adders

Janusz Rajski, Jerzy Tyszer, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

On Utilizing Test Cube Properties to Reduce Test Data Volume Further

Janusz Rajski, Xijiang Lin, 2012, 2012 IEEE 21st Asian Test Symposium.

Empirical failure analysis and validation of fault models in CMOS VLSI

Janusz Rajski, Ashish Pancholy, Larry J. McNaughton, 1990, Proceedings. International Test Conference 1990.

Full-scan LBIST with capture-per-cycle hybrid test points

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2017, 2017 IEEE International Test Conference (ITC).

Low Power Test Compression with Programmable Broadcast-Based Control

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2014, 2014 IEEE 23rd Asian Test Symposium.

Industrial experience with adoption of edt for low-cost test without concessions

Nilanjan Mukherjee, Janusz Rajski, Peter Muhmenthaler, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Embedded deterministic test for low cost manufacturing test

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2002, Proceedings. International Test Conference.

Compactor independent direct diagnosis

Janusz Rajski, Wu-Tung Cheng, Kun-Han Tsai, 2004, 13th Asian Test Symposium.

Fault Diagnosis With Convolutional Compactors

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improving the Resolution of Single-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Clock-domain-aware test for improving pattern compression

Janusz Rajski, Kun-Han Tsai, 2015, VLSI Design, Automation and Test(VLSI-DAT).

ROM fault diagnosis for O(n2) test algorithms

Janusz Rajski, Jerzy Tyszer, Artur Pogiel, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Isometric test compression with low toggling activity

Nilanjan Mukherjee, Sudhakar M. Reddy, Amit Kumar, 2014, 2014 International Test Conference.

Session T1B: Tutorial: SoC testing

Janusz Rajski, Yu Huang, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Modular compactor of test responses

Janusz Rajski, Wojciech Rajski, 2006, 24th IEEE VLSI Test Symposium.

Low power compression of incompatible test cubes

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2010, 2010 IEEE International Test Conference.

A method for concurrent decomposition and factorization of Boolean expressions

Janusz Rajski, Jagadeesh Vasudevamurthy, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Realizing high test quality goals with smart test resource usage

Janusz Rajski, Xinli Gu, Kun-Han Tsai, 2004 .

Staggered ATPG with capture-per-cycle observation test points

Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer, 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

STAR-ATPG: a high speed test pattern generator for large scan designs

Malgorzata Marek-Sadowska, Kuo-Hui Tsai, Janusz Rajski, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

High speed ring generators and compactors of test data [logic IC test]

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Synthesis of X-tolerant convolutional compactors

Janusz Rajski, Jerzy Tyszer, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Minimal area test points for deterministic patterns

Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, 2016, 2016 IEEE International Test Conference (ITC).

Low capture power at-speed test in EDT environment

Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, 2010, 2010 IEEE International Test Conference.

2D test sequence generators

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2003, IEEE Design & Test of Computers.

Hypercompression of Test Patterns

Chen Wang, Janusz Rajski, Jerzy Tyszer, 2018, 2018 IEEE International Test Conference (ITC).

[Plenary talks - 11 abstracts]

Zebo Peng, Hiroshi Iwai, Janusz Rajski, 2014, VLSID 2014.

Embedded test for low cost manufacturing

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2004, 17th International Conference on VLSI Design. Proceedings..

Testing And Applications of Inverter-Free PLAs

Janusz Rajski, Vinod Agarwal, 1987, IEEE Design & Test of Computers.

On testable multipliers for fixed-width data path architectures

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 1995, ICCAD.

On Test Set Preservation of Retimed Circuits

Janusz Rajski, Aiman H. El-Maleh, Wojciech Maly, 1995, 32nd Design Automation Conference.

Synthesis of pattern generators based on cellular automata with phase shifters

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement

Janusz Rajski, Manish Sharma, Martin Keim, 2007, 12th IEEE European Test Symposium (ETS'07).

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits

Sudhakar M. Reddy, Janusz Rajski, Xijiang Lin, 2015, 2015 28th International Conference on VLSI Design.

Fault coverage analysis of RAM test algorithms

Janusz Rajski, Marc Riedel, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Low Shift and Capture Power Scan Tests

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Timing-Aware Multiple-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, ISQED 2008.

Quality assurance in memory built-in self-test tools

Janusz Rajski, Jerzy Tyszer, Justyna Zawada, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Diagnosis withLimited Failure Information

Janusz Rajski, Nagesh Tamarapalli, 2006 .

Finite memory test response compactors for embedded test applications

Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays

Janusz Rajski, Jerzy Tyszer, 1985, IEEE Transactions on Computers.

Convolutional Compactors with Variable Polynomials

Janusz Rajski, Jerzy Tyszer, Artur Pogiel, 2006, Eleventh IEEE European Test Symposium (ETS'06).

Recent advances in logic synthesis with testability

Janusz Rajski, Aiman H. El-Maleh, Jagadeesh Vasudevamurthy, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Finding a common fault response for diagnosis during silicon debug

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Automated synthesis of phase shifters for built-in self-testapplications

Janusz Rajski, Jerzy Tyszer, Nagesh Tamarapalli, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Cell-aware experiences in a high-quality automotive test suite

Friedrich Hapke, Jürgen Schlöffel, Janusz Rajski, 2014, 2014 19th IEEE European Test Symposium (ETS).

Modular logic built-in self-test for IP cores

Janusz Rajski, Jerzy Tyszer, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

A complexity analysis of sequential ATPG

Janusz Rajski, Aiman H. El-Maleh, Wojciech Maly, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Parallel PLA Fault Si ulatioq Based on Boolean Vector %perat ions

Janusz Rajski, Eli Chiprout, Markus Robinson, 1988 .

On necessary and nonconflicting assignments in algorithmic test pattern generation

Janusz Rajski, Henry Cox, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Innovations in test automation

Anand Raghunathan, Janusz Rajski, Jim Sproch, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

On multiple fault coverage and aliasing probability measures

André Ivanov, Vinod K. Agarwal, Janusz Rajski, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

High performance dense ring generators

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2006, IEEE Transactions on Computers.

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

Bernard Courtois, Janusz Rajski, Sybille Hellebrand, 1995, IEEE Trans. Computers.

A method to calculate necessary assignments in algorithmic test pattern generation

Janusz Rajski, Henry Cox, 1990, Proceedings. International Test Conference 1990.

Diagnosis of Failing Scan Cells through Orthogonal Response Compaction

Janusz Rajski, Jerzy Tyszer, Brady Benware, 2011, ETS.

Trimodal Scan-Based Test Paradigm

Chen Wang, Janusz Rajski, Jerzy Tyszer, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Effective Design of Layout-Friendly EDT Decompressor

Nilanjan Mukherjee, Janusz Rajski, Yu Huang, 2020, 2020 IEEE 38th VLSI Test Symposium (VTS).

Multiplicative window generators of pseudo-random test vectors

Janusz Rajski, Jerzy Tyszer, 1996, Proceedings ED&TC European Design and Test Conference.

Design of phase shifters for BIST applications

Janusz Rajski, Jerzy Tyszer, J. Rajski, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Arithmetic built-in self test for high-level synthesis

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Affordable and effective screening of delay defects in ASICs using the inline resistance fault model

Janusz Rajski, Martin Keim, Brady Benware, 2004 .

BIST of PCB interconnects using boundary-scan architecture

Benoit Nadeau-Dostie, Vinod K. Agarwal, Janusz Rajski, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Scan tests with multiple fault activation cycles for delay faults

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2006, 24th IEEE VLSI Test Symposium.

Testing and diagnosis of interconnects using boundary scan architecture

Vinod K. Agarwal, Janusz Rajski, Abu S. M. Hassan, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Generation of correlated random patterns for the complete testing of synthesized multi-level circuits

Janusz Rajski, Stephen Pateras, 1991, 28th ACM/IEEE Design Automation Conference.

Special session 8B — Panel: In-field testing of SoC devices: Which solutions by which players?

Jacob A. Abraham, Janusz Rajski, Matteo Sonza Reorda, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Impact of multiple-detect test patterns on product quality

Janusz Rajski, Kun-Han Tsai, Nagesh Tamarapalli, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Planar high performance ring generators

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Two-dimensional test data decompressor for multiple scan designs

John A. Waicukauski, Janusz Rajski, Jerzy Tyszer, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs

Sudhakar M. Reddy, Amit Kumar, Janusz Rajski, 2013, 2013 22nd Asian Test Symposium.

Software Accelerated Functional Fault Simulation for Data-Path Architectures

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 1995, 32nd Design Automation Conference.

STARBIST: scan autocorrelated random pattern generation

Malgorzata Marek-Sadowska, Janusz Rajski, Sybille Hellebrand, 1997, DAC.

Testing of glue logic interconnects using boundary scan architecture

Benoit Nadeau-Dostie, Vinod K. Agarwal, Janusz Rajski, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

Fault diagnosis in designs with convolutional compactors

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2004, 2004 International Conferce on Test.

Affordable and effective screening of delay defects in ASICs using the inline resistance fault model

Janusz Rajski, Martin Keim, Brady Benware, 2004, 2004 International Conferce on Test.

Systems On Silicon: Design and Test Challenges

Yervant Zorian, Janusz Rajski, J. Borel, 1997, VTS.

On New Class of Test Points and Their Applications

Janusz Rajski, Jerzy Tyszer, Justyna Zawada, 2018, 2018 IEEE International Test Conference (ITC).

Hierarchical functional fault simulation for high-level synthesis

Janusz Rajski, Jerzy Tyszer, Mark Kassab, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Empirical failure analysis and validation of fault models in CMOS VLSI circuits

Janusz Rajski, Ashish Pancholy, Larry J. McNaughton, 1992, IEEE Design & Test of Computers.

Self-test methodology for at-speed test of crosstalk in chip interconnects

Sujit Dey, Janusz Rajski, Xiaoliang Bai, 2000, DAC.

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Ring generators - new devices for embedded test applications

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients

Janusz Rajski, Jerzy Tyszer, J. Rajski, 2003, J. Electron. Test..

Conflict driven techniques for improving deterministic test pattern generation

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Analysis and methodology for multiple-fault diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test pattern compression for a test environment of integrated circuits

Janusz Rajski, Jerzy Tyszer, Mark Kassab, 2000 .

Test Generation for Interconnect Opens

Janusz Rajski, Xijiang Lin, 2008, 2008 IEEE International Test Conference.

Parallel PLA fault simulation based on Boolean vector operations

Janusz Rajski, Eli Chiprout, Markus Robinson, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Design for low test pattern counts

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A test pattern ordering algorithm for diagnosis with truncated fail data

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Digital Testing of ICs for Automotive Applications

Nilanjan Mukherjee, Janusz Rajski, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

On Compacting Test Response Data Containing Unknown Values

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2003, ICCAD.

DFT for high-quality low cost manufacturing test

Janusz Rajski, 2001, Proceedings 10th Asian Test Symposium.

Testability Implications of Performance-Driven Logic Synthesis

Janusz Rajski, Aiman H. El-Maleh, Wojciech Maly, 1995, IEEE Des. Test Comput..

Arithmetic built-in self-test for DSP cores

Janusz Rajski, Jerzy Tyszer, K. Radecka, 1999 .

On Test Points Enhancing Hardware Security

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Cell-Aware Test

Friedrich Hapke, Jürgen Schlöffel, Michael Reese, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2011, 2011 IEEE International Test Conference.

Autonomous Scan Patterns for Laser Voltage Imaging

Janusz Rajski, Wu-Tung Cheng, Grzegorz Mrugalski, 2019 .

Embedded Deterministic Test Points

Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parameterizable testing scheme for FIR filters

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 1997, Proceedings International Test Conference 1997.

A method of fault analysis for test generation and fault diagnosis

Janusz Rajski, Henry Cox, J. Rajski, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Diagnosis with Limited Failure Information

Janusz Rajski, Wu-Tung Cheng, Nagesh Tamarapalli, 2006, 2006 IEEE International Test Conference.

Fault diagnosis in designs with convolutional compactors

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2004 .

Stuck-open and transition fault testing in CMOS complex gates

Janusz Rajski, Henry Cox, J. Rajski, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Comparative study of CA-based PRPGs and LFSRs with phase shifters

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Scan-Encoded Test Pattern Generation for BIST

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 1997, ITC.

Embedded Test Technology - Brief History, Current Status, and Future Directions

Janusz Rajski, 2005, 14th Asian Test Symposium (ATS'05).

Logic Diagnosis and Yield Learning

Janusz Rajski, 2007, DDECS.

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs

Janusz Rajski, Nilanjan Mukherjee, Grzegorz Mrugalski, 2014, 2014 IEEE 23rd Asian Test Symposium.

Scan Integrity Tests for EDT Compression

Janusz Rajski, Wu-Tung Cheng, Grzegorz Mrugalski, 2020, IEEE Design & Test.

Low power test application with selective compaction in VLSI designs

Janusz Rajski, Jerzy Tyszer, Dariusz Czysz, 2012, 2012 IEEE International Test Conference.

X-Tolerant Tunable Compactor for In-System Test

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2020, 2020 IEEE International Test Conference (ITC).

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors

Abhijit Chatterjee, Miodrag Potkonjak, Adit D. Singh, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Enhancing Delay Fault Coverage through Low Power Segmented Scan

Irith Pomeranz, Bashir M. Al-Hashimi, Janusz Rajski, 2006, ETS.

Test Generation in the Presence of Timing Exceptions and Constraints

Dhiraj Goswami, Janusz Rajski, Kun-Han Tsai, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns

Janusz Rajski, Jerzy Tyszer, Sanjay Gupta, 1996, IEEE Trans. Computers.

Low-Power Scan Operation in Test Compression Environment

Janusz Rajski, Jerzy Tyszer, Xijiang Lin, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Recursive Pseudoexhaustive Test Pattern Generation

Janusz Rajski, Jerzy Tyszer, 1993, IEEE Trans. Computers.

Embedded deterministic test for low-cost manufacturing

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2003, IEEE Design & Test of Computers.

Test Time Reduction in EDT Bandwidth Management for SoC Designs

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Realizing high test quality goals with smart test resource usage

Janusz Rajski, Xinli Gu, Jan Arild Tofte, 2004, 2004 International Conferce on Test.

X-Press Compactor for 1000x Reduction of Test Data

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2006, 2006 IEEE International Test Conference.

Hybrid Hierarchical and Modular Tests for SoC Designs

Yu Huang, Yuan Zuo, Rui Li, 2015, 2015 IEEE 24th North Atlantic Test Workshop.

Time and Area Optimized Testing of Automotive ICs

Janusz Rajski, Jerzy Tyszer, Nilanjan Mukherjee, 2020 .

Defect Aware to Power Conscious Tests - The New DFT Landscape

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2009, 2009 22nd International Conference on VLSI Design.

Test Responses Compaction in Accumulators with

Janusz Rajski, Jerzy Tyszer, J. Rajski, 1993 .

Cell-aware Production test results from a 32-nm notebook processor

Friedrich Hapke, Jürgen Schlöffel, Michael Reese, 2012, 2012 IEEE International Test Conference.

Test generator with preselected toggling for low power built-in self-test

Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

Transistor stuck-on fault detection tests for digital CMOS circuits

Sudhakar M. Reddy, Janusz Rajski, Xijiang Lin, 2016, 2016 21th IEEE European Test Symposium (ETS).

High-Speed On-Chip Event Counters for Embedded Systems

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2009, 2009 22nd International Conference on VLSI Design.

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating

Sudhakar M. Reddy, Janusz Rajski, Elham K. Moghaddam, 2011, 2011 Asian Test Symposium.

Diagnosis of Scan Cells in BIST Environment

Janusz Rajski, Jerzy Tyszer, 1999, IEEE Trans. Computers.

Improving the proportion of at-speed tests in scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Bandwidth-aware test compression logic for SoC designs

Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer, 2012, 2012 17th IEEE European Test Symposium (ETS).

Isometric Test Data Compression

Nilanjan Mukherjee, Sudhakar M. Reddy, Amit Kumar, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Logic BIST With Capture-Per-Clock Hybrid Test Points

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Deterministic Stellar BIST for In-System Automotive Test

Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, 2018, 2018 IEEE International Test Conference (ITC).

Test compression - real issues and matching solutions

Janusz Rajski, 2005, IEEE International Conference on Test, 2005..

Test Time and Area Optimized BrST Scheme for Automotive ICs

Nilanjan Mukherjee, Janusz Rajski, Daniel Tille, 2019, 2019 IEEE International Test Conference (ITC).

Reduced ATE Interface for High Test Data Compression

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2011, 2011 Sixteenth IEEE European Test Symposium.

New Test Data Decompressor for Low Power Applications

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Low-Power Programmable PRPG With Test Compression Capabilities

Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Delay-fault testability preservation of the concurrent decomposition and factorization transformations

Janusz Rajski, Aiman H. El-Maleh, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits

Janusz Rajski, Fadi Maamari, 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

Diagnosis of hold time defects

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

At-speed scan test with low switching activity

Sudhakar M. Reddy, Janusz Rajski, Elham K. Moghaddam, 2010, 2010 28th VLSI Test Symposium (VTS).

Behavior and testability preservation under the retiming transformation

Janusz Rajski, Aiman H. El-Maleh, Wojciech Maly, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Multiple fault diagnosis using n-detection tests

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2003, Proceedings 21st International Conference on Computer Design.

A method of fault simulation based on stem regions

Janusz Rajski, Fadi Maamari, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Deterministic Stellar BIST for Automotive ICs

Sudhakar M. Reddy, Nilanjan Mukherjee, Janusz Rajski, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The dynamic reduction of fault simulation

Janusz Rajski, Fadi Maamari, 1990, Proceedings. International Test Conference 1990.

New procedures to identify redundant stuck-at faults and removal of redundant logic

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2007, IEEE Design & Test of Computers.

Fault Diagnosis in Memory BIST Environment with Non-march Tests

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2011, 2011 Asian Test Symposium.

Low Power Scan Shift and Capture in the EDT Environment

Janusz Rajski, Jerzy Tyszer, Xijiang Lin, 2008, 2008 IEEE International Test Conference.

Convolutional compaction of test responses

Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

On the diagnostic properties of linear feedback shift registers

Janusz Rajski, Jerzy Tyszer, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A process for the synthesis of linear finite state machine

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2000 .

On using implied values in EDT-based test compression

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Test response compactor with programmable selector

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Test point insertion in hybrid test compression/LBIST architectures

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2016, 2016 IEEE International Test Conference (ITC).

On Deploying Scan Chains for Data Storage in Test Compression Environment

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2013, IEEE Design & Test.

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels

Kuen-Jong Lee, Janusz Rajski, Yu Huang, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

TestResponse Compactor withProgrammable Selector

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2006 .

Accumulator-based compaction for built-in self test of data-path architectures

Janusz Rajski, Jerzy Tyszer, M. Kassab, 1992, Proceedings First Asian Test Symposium (ATS `92).

Test pattern generation based on arithmetic operations

Janusz Rajski, Jerzy Tyszer, Sanjay Gupta, 1994, ICCAD.

Delay fault diagnosis for nonrobust test

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs

Janusz Rajski, Reinhard Meier, Geir Eide, 2020, 2020 IEEE International Test Conference (ITC).

Ring Generator: An Ultimate Linear Feedback Shift Register

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2011, Computer.

Test data compression and compaction for embedded test of nanometer technology designs

Janusz Rajski, Jerzy Tyszer, 2003, Proceedings 21st International Conference on Computer Design.

On Compacting Test Response Data Containing Unknown Values

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2003, ICCAD 2003.

Compressed pattern diagnosis for scan chain failures

Janusz Rajski, Wu-Tung Cheng, Yu Huang, 2005, IEEE International Conference on Test, 2005..

Enhancing Delay Fault Coverage through Low Power Segmented Scan

Irith Pomeranz, Sudhakar M. Reddy, Bashir M. Al-Hashimi, 2006, Eleventh IEEE European Test Symposium (ETS'06).

A self-reconfiguration scheme for fault-tolerant VLSI processor arrays

Janusz Rajski, S. Pateras, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

A self-driven test structure for pseudorandom testing of non-scan sequential circuits

Janusz Rajski, Fidel Muradali, J. Rajski, 1996, Proceedings of 14th VLSI Test Symposium.

Cell-aware analysis for small-delay effects and production test results from different fault models

Friedrich Hapke, Jürgen Schlöffel, Michael Reese, 2011, 2011 IEEE International Test Conference.

On Compaction Utilizing Inter and Intra-Correlation of Unknown States

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On Cyclic Scan Integrity Tests for EDT-based Compression

Janusz Rajski, Wu-Tung Cheng, Grzegorz Mrugalski, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

Highly X-Tolerant Selective Compaction of Test Responses

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2009, 2009 27th IEEE VLSI Test Symposium.

Propagation delay fault: a new fault model to test delay faults

Janusz Rajski, Xijiang Lin, 2005, ASP-DAC.

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring

Wojciech Maly, Janusz Rajski, Jitendra Khare, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Logic BIST for large industrial designs: real issues and case studies

Janusz Rajski, Nagesh Tamarapalli, Graham Hetherington, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

A fault simulation method based on stem regions

Janusz Rajski, Fadi Maamari, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

The impacts of untestable defects on transition fault testing

Janusz Rajski, Xijiang Lin, 2006, 24th IEEE VLSI Test Symposium.

GEMINI-a logic system for fault diagnosis based on set functions

Janusz Rajski, 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis

Janusz Rajski, Manish Sharma, Nagesh Tamarapalli, 2006, 2006 IEEE International Test Conference.

Decompression of test data using variable-length seed LFSRs

Janusz Rajski, Jerzy Tyszer, Nadime Zacharia, 1995, Proceedings 13th IEEE VLSI Test Symposium.

An efficient and effective methodology on the multiple fault diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Test Challenges of Nanometer Technology

Janusz Rajski, 2003, ITC.

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2006, 2006 IEEE International Test Conference.

Efficient Prognostication of Pattern Count with Different Input Compression Ratios

Kuen-Jong Lee, Janusz Rajski, Yu Huang, 2020, 2020 IEEE European Test Symposium (ETS).

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs"

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automated synthesis of large phase shifters for built-in self-test

Janusz Rajski, Jerzy Tyszer, Nagesh Tamarapalli, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

Janusz Rajski, Jerzy Tyszer, Brady Benware, 2011, J. Electron. Test..

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults

Janusz Rajski, Wu-Tung Cheng, Xijiang Lin, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Defect aware test patterns

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2005, Design, Automation and Test in Europe.

A unified fault model and test generation procedure for interconnect opens and bridges

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2005, European Test Symposium (ETS'05).

VLSI Signal Processing in FPGAs

Janusz Rajski, Jerzy Tyszer, Sanjay Patel, 1999, VLSI Design.

Diagnosis with convolutional compactors in presence of unknown states

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2005, IEEE International Conference on Test, 2005..

The detection of small size multiple faults by single fault test sets n programmable logic arrays

Janusz Rajski, Jerzy Tyszer, 1984, Fehlertolerierende Rechensysteme.

DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies

Friedrich Hapke, Janusz Rajski, Andreas Glowatz, 2018, 2018 IEEE International Test Conference (ITC).

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

EDT Bandwidth Management in SoC Designs

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low power programmable PRPG with enhanced fault coverage gradient

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2012, 2012 IEEE International Test Conference.

Compression based on deterministic vector clustering of incompatible test cubes

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2009, 2009 International Test Conference.

Low power compression utilizing clock-gating

Sudhakar M. Reddy, Janusz Rajski, Elham K. Moghaddam, 2011, 2011 IEEE International Test Conference.

Scan-Based Tests with Low Switching Activity

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2007, IEEE Design & Test of Computers.

Adaptive Low Shift Power Test Pattern Generator for Logic BIST

Janusz Rajski, Xijiang Lin, 2010, 2010 19th IEEE Asian Test Symposium.

A deterministic BIST scheme based on EDT-compressed test patterns

Janusz Rajski, Jerzy Tyszer, Lukasz Rybak, 2015, 2015 IEEE International Test Conference (ITC).

Nanometer design: what are the requirements for manufacturing test?

Janusz Rajski, Kan Thapar, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Embedded deterministic test

Janusz Rajski, 2008 .

Low Power Decompressor and PRPG with Constant Value Broadcast

Janusz Rajski, Jerzy Tyszer, Masahiro Takakura, 2011, 2011 Asian Test Symposium.

We Have Got Compression, What Next?

Janusz Rajski, 2009, ETS.

Delay-fault diagnosis using timing information

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Timing-Aware Multiple-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On New Test Points for Compact Cell-Aware Tests

Nilanjan Mukherjee, Friedrich Hapke, Janusz Rajski, 2016, IEEE Design & Test.

Conflict driven techniques for improving deterministic test pattern generation

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2002, ICCAD 2002.

Timing-Aware Multiple-Delay-Fault Diagnosis

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Star test: the theory and its applications

Malgorzata Marek-Sadowska, Janusz Rajski, Kun-Han Tsai, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Enabling embedded memory diagnosis via test response compression

Wojciech Maly, Janusz Rajski, Jitendra Khare, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

A scalable method for the generation of small test sets

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

On Linear Dependencies in Subspaces of LFSR-Generated Sequences

Janusz Rajski, Jerzy Tyszer, 1996, IEEE Trans. Computers.

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test Compression Improvement with EDT Channel Sharing in SoC Designs

Yu Huang, Kun Young Chung, Janusz Rajski, 2014, 2014 IEEE 23rd North Atlantic Test Workshop.

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2006, 2006 IEEE International Test Conference.

Complexity of sequential ATPG

Janusz Rajski, Aiman H. El-Maleh, Wojciech Maly, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Convolutional compaction-driven diagnosis of scan failures

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2005, European Test Symposium (ETS'05).

Using dynamic shift to reduce test data volume in high-compression designs

Janusz Rajski, Xijiang Lin, Mark Kassab, 2014, 2014 19th IEEE European Test Symposium (ETS).

Linear independence as evaluation criterion for two-dimensional test pattern generators

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2000, Proceedings 18th IEEE VLSI Test Symposium.

New test compression scheme based on low power BIST

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2013, 2013 18th IEEE European Test Symposium (ETS).

Dynamic channel allocation for higher EDT compression in SoC designs

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2010, 2010 IEEE International Test Conference.

Built-In Self-Test for Systems on Silicon

Janusz Rajski, Jerzy Tyszer, Sanjay Patel, 1999 .

Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers

Bernard Courtois, Janusz Rajski, Sybille Hellebrand, 1992 .

Test Pattern Generation Based On Arithmetic Operations

Janusz Rajski, Jerzy Tyszer, Sanjay Gupta, 1994, IEEE/ACM International Conference on Computer-Aided Design.

TestGeneration forInterconnect Opens

Janusz Rajski, Xijiang Lin, 2008 .

BIST-Based Fault Diagnosis for Read-Only Memories

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On static test compaction and test pattern ordering for scan designs

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Testability preserving transformations in multi-level logic synthesis

Janusz Rajski, Jagadeesh Vasudevamurthy, 1990, Proceedings. International Test Conference 1990.

Embedded deterministic test

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Delay-fault testability preservation of the concurrent decomposition and factorization transformations

Janusz Rajski, Aiman H. El-Maleh, 1994, Proceedings of IEEE VLSI Test Symposium.

Low Cost Hypercompression of Test Data

Janusz Rajski, Jerzy Tyszer, Chen Wang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design of Testable Multipliers for Fixed-Width Data Paths

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 1997, IEEE Trans. Computers.

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations

Chen Wang, Kuen-Jong Lee, Janusz Rajski, 2020, 2020 IEEE International Test Conference (ITC).

Hardware Protection via Logic Locking Test Points

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2008, 2008 IEEE International Test Conference.

Hardware-Software Co-Design for Test: It's the Last Straw!

Niraj K. Jha, Najmi T. Jarwala, Christos A. Papachristou, 1996, VTS.

Low Power Embedded Deterministic Test

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Testing Properties and Applications of Inverter-Free PLA's

Vinod K. Agarwal, Janusz Rajski, 1985, ITC.

EDT bandwidth management - Practical scenarios for large SoC designs

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2013, 2013 IEEE International Test Conference (ITC).

The testability-preserving concurrent decomposition and factorization of Boolean expressions

Janusz Rajski, Jagadeesh Vasudevamurthy, J. Rajski, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Testing Schemes for FIR Filter Structures

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2001, IEEE Trans. Computers.

N-distinguishing Tests for Enhanced Defect Diagnosis

Gang Chen, Irith Pomeranz, Sudhakar M. Reddy, 2009, 2009 Asian Test Symposium.

Fault diagnosis for embedded read-only memories

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2009, 2009 International Test Conference.

Test Data Decompression for Multiple Scan Designs with Boundary Scan

Janusz Rajski, Jerzy Tyszer, Nadime Zacharia, 1998, IEEE Trans. Computers.

Diagnosis of Failing Scan Cells through Orthogonal Response Compaction

Janusz Rajski, Jerzy Tyszer, Brady Benware, 2010, 2011 Sixteenth IEEE European Test Symposium.

Fault diagnosis in scan-based BIST

Janusz Rajski, Jerzy Tyszer, 1997, Proceedings International Test Conference 1997.

Fault diagnosis of TSV-based interconnects in 3-D stacked designs

Janusz Rajski, Jerzy Tyszer, J. Rajski, 2013, 2013 IEEE International Test Conference (ITC).

Isolation of Failing Scan Cells through Convolutional Test Response Compaction

Chen Wang, Janusz Rajski, Grzegorz Mrugalski, 2007, J. Electron. Test..

Cube-Contained Random Patterns and their Application to the Complete Testing of Synthesized Multi-le

Janusz Rajski, Stephen Pateras, 1991, 1991, Proceedings. International Test Conference.

Test responses compaction in accumulators with rotate carry adders

Janusz Rajski, Jerzy Tyszer, J. Rajski, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Constructive multi-phase test point insertion for scan-based BIST

Janusz Rajski, Nagesh Tamarapalli, J. Rajski, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Efficient Test Compression Configuration Selection

Sudhakar M. Reddy, Janusz Rajski, Mark Kassab, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Defect-Oriented Test: Effectiveness in High Volume Manufacturing

Friedrich Hapke, Janusz Rajski, Andreas Glowatz, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

LBIST for Automotive ICs with Enhanced Test Generation

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Convolutional Compaction-Based MRAM Fault Diagnosis

Janusz Rajski, Jerzy Tyszer, Martin Keim, 2021, 2021 IEEE European Test Symposium (ETS).

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On testable multipliers for fixed-width data path architectures

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

An E cient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers

Janusz Rajski, Sybille Hellebrand, S. Hellebrand, 1993 .

Improved algorithms for constructive multi-phase test point insertion for scan based BIST

Sudhakar M. Reddy, Janusz Rajski, Nadir Z. Basturkmen, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.