Haruyoshi Yonekawa

In-memory area-efficient signal streaming processor design for binary neural networks

Tetsuya Asai, Hiroki Nakahara, Shimpei Sato, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)

Hiroki Nakahara, Masato Motomura, Hisashi Iwamoto, 2017, FPGA.

An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA

Hiroki Nakahara, Shimpei Sato, Haruyoshi Yonekawa, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

A memory-based realization of a binarized deep convolutional neural network

Tsutomu Sasao, Hiroki Nakahara, Masato Motomura, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Tadahiro Kuroda, Tetsuya Asai, Hiroki Nakahara, 2018, IEEE Journal of Solid-State Circuits.

A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA

Hiroki Nakahara, Tomoya Fujii, Shimpei Sato, 2018, FPGA.

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers

Hiroki Nakahara, Tomoya Fujii, Shimpei Sato, 2019, IEICE Trans. Inf. Syst..

BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

Tadahiro Kuroda, Tetsuya Asai, Hiroki Nakahara, 2017, 2017 Symposium on VLSI Circuits.

A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA

Tomoya Fujii, Hiroyuki Nakahara, Masayuki Shimoda, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA

Hiroki Nakahara, Haruyoshi Yonekawa, Hiroki Nakahara, 2017, 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor

Hiroki Nakahara, Shimpei Sato, Haruyoshi Yonekawa, 2018, 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL).