Marcelo Antonio Pavanello

发表

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

Maud Vinet, Bruna Cardoso Paz, Renan Trevisoli Doria, 2017, Microelectron. Reliab..

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

Denis Flandre, Marcelo Antonio Pavanello, Rodrigo Trevisoli Doria, 2008, Microelectron. J..

Improved Source-Follower Buffer Implementation by Using Graded-Channel SOI nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2008 .

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Renan Trevisoli Doria, Marcelo Antonio Pavanello, Cor Claeys, 2012, Microelectron. Reliab..

Analog circuit design using graded-channel SOI nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, João Antonio Martino, 2001, Symposium on Integrated Circuits and Systems Design.

Graded-channel SOI NMOSFET and its potential to analog applications

Denis Flandre, Marcelo Antonio Pavanello, Joao Antonio Martino, 1999 .

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2008 .

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

Denis Flandre, Bruna Cardoso Paz, Marcelo Antonio Pavanello, 2013, Microelectron. Reliab..

Analog performance of graded-channel SOI nMOSFETs at low temperatures

Denis Flandre, Marcelo Antonio Pavanello, Joao Antonio Martino, 2002 .

Impact of the Graded-Channel Architecture on Double Gate Transistors for High-Performance Analog Applications

Denis Flandre, Marcelo Antonio Pavanello, Jean-Pierre Raskin, 2003 .

A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2013 .

Study of Matching Properties of Graded-Channel SOI MOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2008 .

An explicit multi-exponential model for semiconductor junctions with series and shunt resistances

Juan Muci, Marcelo Antonio Pavanello, Francisco J. García-Sánchez, 2011, Microelectron. Reliab..

Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS

Denis Flandre, Marcelo Antonio Pavanello, João Antonio Martino, 2006, Microelectron. J..

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

Marcelo Antonio Pavanello, Antonio Cerdeira, Magali Estrada, 2013 .

Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K

Jean-Pierre Colinge, Marcelo Antonio Pavanello, Joao Antonio Martino, 1997 .

Submicrometer graded-channel SOI MOSFET modeling for low temperature analog circuit design

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2006 .

Impact of temperature reduction and channel engineering on the linearity of FD SOI nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Cor Claeys, 2009 .

Analytical Modeling of Double Gate Graded-Channel SOI Transistors for Analog Applications

Denis Flandre, Marcelo Antonio Pavanello, Antonio L. Cerdeira, 2009 .

Comparison of Asymmetric Self-Cascode and Graded-Channel Structures for High Performance Analog SOI MOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2012 .

Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, João Antonio Martino, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

Evaluation of graded-channel SOI MOSFET operation at high temperatures

Marcelo Antonio Pavanello, João Antonio Martino, Milene Galeti, 2006, Microelectron. J..

Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2016, IET Circuits Devices Syst..

A physically-based continuous model for graded-channel SOI MOSFET

Denis Flandre, Marcelo Antonio Pavanello, Benjamin Iniguez, 2002 .

Analog performance of strained SOI nanowires down to 10K

Maud Vinet, Bruna Cardoso Paz, Mikaël Casse, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

A new method for junctionless transistors parameters extraction

Renan Trevisoli Doria, Sylvain Barraud, Marcelo Antonio Pavanello, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

Denis Flandre, Marcelo Antonio Pavanello, João Antonio Martino, 2006, Microelectron. J..

Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Joao Antonio Martino, 2000 .

Implementation of High Performance Operational Transconductance Amplifiers Using Graded-Channel SOI NMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Salvador Pinillos Gimenez, 2005 .

Drain current model for short-channel triple gate junctionless nanowire transistors

Bruna Cardoso Paz, Mikaël Casse, Sylvain Barraud, 2016, Microelectron. Reliab..

Modeling of Thin-Film Lateral SOI PIN Diodes with an Alternative Multi-Branch Explicit Current Model

Denis Flandre, Juan Muci, Marcelo Antonio Pavanello, 2012 .

Performance of Common-Source, Cascode and Wilson Current Mirrors Implemented with Graded Channel SOI nMOSFETs in a Wide Temperature Range

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2009 .

Low Temperature and Channel Engineering Influence on the Behavior of Analog Source-Follower Buffers

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2008 .

Compact core model for Symmetric Double-Gate Junctionless Transistors

Marcelo Antonio Pavanello, Antonio Cerdeira, Magali Estrada, 2014 .

Analog performance and application of graded-channel fully depleted SOI MOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Joao Antonio Martino, 2000 .

Improved current mirror output performance by using graded-channel SOI nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Joao A. Martino, 2001 .

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Maud Vinet, Sylvain Barraud, Olivier Faynot, 2021, ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC).

Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors

Marcelo Antonio Pavanello, Antonio Cerdeira, Joaquín Alvarado, 2009 .

A New Method for Series Resistance Extraction of Nanometer MOSFETs

Maud Vinet, Sylvain Barraud, Gilles Reimbold, 2017, IEEE Transactions on Electron Devices.

Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

Maud Vinet, Sylvain Barraud, Gilles Reimbold, 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Joao Antonio Martino, 2000, Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474).

Simulation of a Miller OpAmp with FinFETs at High Temperatures

Marcelo Antonio Pavanello, A. Cerdeira, Esteban Contreras, 2012 .

The zero temperature coefficient in junctionless nanowire transistors

Marcelo Antonio Pavanello, Isabelle Ferain, Michelly de Souza, 2012 .

Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2014, IEEE Transactions on Electron Devices.

Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

Denis Flandre, Marcelo Antonio Pavanello, Joao Antonio Martino, 2000 .

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Sylvain Barraud, Marcelo Antonio Pavanello, Rodrigo Trevisoli Doria, 2019, Microelectronic Engineering.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Marcelo Antonio Pavanello, Cor Claeys, Rita Rooyackers, 2008 .

The low-frequency noise behaviour of graded-channel SOI nMOSFETs

Denis Flandre, Marcelo Antonio Pavanello, Eddy Simoen, 2007 .

Compact model for short-channel symmetric double-gate junctionless transistors

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Antonio Cerdeira, 2015 .

Impact of the Series Resistance in the I-V Characteristics of nMOS Junctionless Nanowire Transistors

Marcelo Antonio Pavanello, Renan Trevisoli, Rodrigo T. Doria, 2011 .

Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short Wavelengths

Denis Flandre, Marcelo Antonio Pavanello, Michelly de Souza, 2011 .

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Marcelo Antonio Pavanello, Michelly de Souza, Renan Trevisoli, 2015 .

From double to triple gate: Modeling junctionless nanowire transistors

Sylvain Barraud, Gilles Reimbold, Olivier Faynot, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Antonio Cerdeira, 2016 .

An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics

Denis Flandre, Marcelo Antonio Pavanello, Joao Antonio Martino, 1999 .

Direct determination of threshold condition in DG-MOSFETs from the gm/ID curve

Marcelo Antonio Pavanello, Carlos Galup-Montoro, Ana Isabela Araujo Cunha, 2011 .

Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

Marcelo Antonio Pavanello, Cor Claeys, Eddy Simoen, 2007 .

Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion

Abhinav Kranti, Jean-Pierre Colinge, Marcelo Antonio Pavanello, 2011 .

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Maud Vinet, Sylvain Barraud, Olivier Faynot, 2017 .