N. Togawa

发表

Regular Paper Scan Vulnerability in Elliptic Curve

T. Ohtsuki, M. Yanagisawa, Ryuta Nara, 2011 .

Implementation of Motion Estimation IP Core for MPEG Encoder

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2001 .

Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists

Nozomu Togawa, Seira Hidano, Shinsaku Kiyomoto, 2021, J. Inf. Process..

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Nozomu Togawa, Masao Yanagisawa, Yuichiro Miyaoka, 2001 .

QuDASH: Quantum-inspired rate adaptation approach for DASH video streaming

J. Katto, N. Togawa, Bo Wei, 2022, ArXiv.

Reconfigurable adaptive FEC system with interleaving

Nozomu Togawa, Satoshi Goto, Takeshi Ikenaga, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

A hardware/software partitioning algorithm for SIMD processor cores

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

A Hardware / Software Cosynthesis System for CAM Processors

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2001 .

A Three-Stage Annealing Method Solving Slot-Placement Problems Using an Ising Machine

N. Togawa, Yoshinori Tomita, Matthieu Parizy, 2021, IEEE Access.

Cardinality Constrained Portfolio Optimization on an Ising Machine

P. Sadowski, N. Togawa, Matthieu Parizy, 2022, 2022 IEEE 35th International System-on-Chip Conference (SOCC).

Indoor Navigation Based on Pedestrians ’ Viewpoints

M. Yanagisawa, N. Togawa, Ryota Iwanaji, 2016 .

Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching

Nozomu Togawa, Masao Yanagisawa, Yukiyasu Tsunoo, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multi-Objective Trip Planning Based on Ant Colony Optimization Utilizing Trip Records

N. Togawa, Etsushi Saeki, Siya Bao, 2022, IEEE Access.

A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models

N. Togawa, Ryotaro Negishi, Tatsuki Kurihara, 2022, 2022 IEEE 12th International Conference on Consumer Electronics (ICCE-Berlin).

Towards optimization of photonic-crystal surface-emitting lasers via quantum annealing.

S. Noda, K. Ishizaki, Yuya Seki, 2022, Optics express.

A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines

Nozomu Togawa, Daisuke Oku, Kotaro Terada, 2019, IEICE Trans. Inf. Syst..

Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine

Nozomu Togawa, Kensuke Tamura, Shu Tanaka, 2021, IEEE Access.

Dynamical process of a bit-width reduced Ising model with simulated annealing

N. Togawa, Shuta Kikuchi, Shu Tanaka, 2023, 2304.12796.

How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins

Nozomu Togawa, Daisuke Oku, Masashi Tawada, 2020, IEEE Transactions on Computers.

An Ising Machine-Based Solver for Visiting-Route Recommendation Problems in Amusement Parks

Nozomu Togawa, Shu Tanaka, Yosuke Mukasa, 2021, IEICE Trans. Inf. Syst..

Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations

Nozomu Togawa, Kazushi Kawamura, Sho Kanamaru, 2021, IEICE Trans. Inf. Syst..

Visiting-Route Recommendation in Amusement Parks and its Evaluations by an Ising Machine

Nozomu Togawa, Shu Tanaka, Yosuke Mukasa, 2021, 2021 IEEE International Conference on Consumer Electronics (ICCE).

Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines

Nozomu Togawa, Shu Tanaka, Tatsuhiko Shirai, 2020, IEEE Access.

Theory of Ising Machines and a Common Software Platform for Ising Machines

Nozomu Togawa, Shu Tanaka, Yoshiki Matsuda, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine

Hidetoshi Matsuoka, Nozomu Togawa, Kazushi Kawamura, 2019, 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin).

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Nozomu Togawa, Masao Yanagisawa, Hiromine Yoshihara, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution

Nozomu Togawa, Masao Yanagisawa, Hiromine Yoshihara, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Soft error tolerant latch designs with low power consumption (invited paper)

Saki Tajima, Youhua Shi, Nozomu Togawa, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Effective Parallel Algorithm for GPGPU-Accelerated Explicit Routing Optimization

Eiji Oki, Nozomu Togawa, Naoaki Yamanaka, 2014, 2015 IEEE Global Communications Conference (GLOBECOM).

Effective write-reduction method for MLC non-volatile memory

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A write-reducing and error-correcting code generation method for non-volatile memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board

Nozomu Togawa, Kazushi Kawamura, Kento Hasegawa, 2019, 2019 International Conference on Field-Programmable Technology (ICFPT).

A high-level synthesis system for digital signal processing based on enumerating data-flow graphs

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

An Indoor Positioning Method using Smartphone and Smartwatch Independent of Carrying Modes

Nozomu Togawa, Tomoya Wakaizumi, N. Togawa, 2021, 2021 IEEE International Conference on Consumer Electronics (ICCE).

R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training

Seira Hidano, S. Kiyomoto, N. Togawa, 2022, IEEE Transactions on Computers.

Node-wise Hardware Trojan Detection Based on Graph Learning

Seira Hidano, N. Togawa, Kento Hasegawa, 2021, IEEE Transactions on Computers.

Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists

Nozomu Togawa, Seira Hidano, Shinsaku Kiyomoto, 2019, CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS.

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests

Nozomu Togawa, Tatsuki Kurihara, N. Togawa, 2021, 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS).

A hardware-Trojan classification method utilizing boundary net structures

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2018, 2018 IEEE International Conference on Consumer Electronics (ICCE).

Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Nozomu Togawa, Masao Yanagisawa, Masashi Shio, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Capacitance Measurement of Running Hardware Devices and its Application to Malicious Modification Detection

Nozomu Togawa, Kento Hasegawa, Makoto Nishizawa, 2018, 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Hardware Trojans classification for gate-level netlists based on machine learning

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Nozomu Togawa, Masao Yanagisawa, Takashi Takenaka, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines

Nozomu Togawa, Masashi Tawada, Shu Tanaka, 2020, 2020 IEEE International Conference on Consumer Electronics (ICCE).

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Nozomu Togawa, Satoshi Goto, Takeshi Ikenaga, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Power-efficient LDPC code decoder architecture

Nozomu Togawa, Satoshi Goto, Takeshi Ikenaga, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule

Nozomu Togawa, Satoshi Goto, Takeshi Ikenaga, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule

Nozomu Togawa, Satoshi Goto, Takeshi Ikenaga, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Nozomu Togawa, Takeshi Ikenaga, Tatsuyuki Ishikawa, 2005, 2005 International Conference on Computer Design.

An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines

Nozomu Togawa, Siya Bao, Masashi Tawada, 2021, 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2019, ICIS.

Hardware Trojan Detection Utilizing Machine Learning Approaches

Youhua Shi, Nozomu Togawa, Kento Hasegawa, 2018, 2018 17th IEEE International Conference On Trust, Security And Privacy In Computing And Communications/ 12th IEEE International Conference On Big Data Science And Engineering (TrustCom/BigDataSE).

Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach

Nozomu Togawa, Masao Yanagisawa, Yuki Kobayashi, 2018, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

Instruction set and functional unit synthesis for SIMD processor cores

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Area/delay estimation for digital signal processor cores

M. Yanagisawa, T. Ohtsuki, Y. Miyaoka, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

A hardware/software partitioning algorithm for processor cores of digital signal processing

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Scan-based attack against elliptic curve cryptosystems

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances

N. Togawa, Masashi Tawada, Yuta Atobe, 2022, IEEE Transactions on Computers.

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures

Masao Yanagisawa, Nozomu Togawa, Kento Hasegawa, 2020, IEICE Trans. Inf. Syst..

Trip Planning Based on subQUBO Annealing

N. Togawa, Keisuke Fukada, Siya Bao, 2023, IEEE Access.

Hybrid Optimization Method Using Simulated-Annealing-Based Ising Machine and Quantum Annealer

N. Togawa, Shuta Kikuchi, Shu Tanaka, 2023, Journal of the Physical Society of Japan.

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Post-processing variationally scheduled quantum algorithm for constrained combinatorial optimization problems

N. Togawa, T. Shirai, 2023, 2309.08120.

A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output

N. Togawa, Masashi Tawada, Yuta Yachi, 2023, 2023 IEEE 36th International System-on-Chip Conference (SOCC).

Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines

N. Togawa, T. Shirai, 2023, IEEE Transactions on Computers.

Multi-Spin-Flip Engineering in an Ising Machine

N. Togawa, T. Shirai, 2023, IEEE Transactions on Computers.

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2018, IPSJ Trans. Syst. LSI Des. Methodol..

A hardware/software cosynthesis system for digital signal processor cores with two types of register files

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2000 .

Maple: A Simultaneous Technology Mapping, Placement, And Global Routing Algorithm For Field-programmable Gate Arrays

Nozomu Togawa, Tatsuo Ohtsuki, Masao Sato, 1994, IEEE/ACM International Conference on Computer-Aided Design.

A Constrained Graph Coloring Solver Based on Ising Machines

N. Togawa, Siya Bao, Junji Teramoto, 2023, 2023 IEEE International Conference on Consumer Electronics (ICCE).

A Quasi-Initial Solution Giving Method for Ising Machines by Controlling External Magnetic Field Coefficients

N. Togawa, K. Ohno, Junji Teramoto, 2023, 2023 IEEE International Conference on Consumer Electronics (ICCE).

A Multiple Coefficients Trial Method to Solve Combinatorial Optimization Problems for Simulated-annealing-based Ising Machines

Nozomu Togawa, Daisuke Oku, Shu Tanaka, 2019, 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin).

Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines

Nozomu Togawa, Junya Arai, Masashi Tawada, 2019, 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin).

Efficient Ising Model Mapping to Solving Slot Placement Problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2019, 2019 IEEE International Conference on Consumer Electronics (ICCE).

An Ising model mapping to solve rectangle packing problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems

T. Ohtsuki, N. Togawa, M. Sato, 1995 .