T. Yao

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

T. Miyashita, Masaki Yamabe, Tetsu Tanaka, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Local flare effects and correction in ArF lithography

S. Asai, K. Ogino, Y. Machida, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).