A. Acosta

CMOS inverter maximum frequency of operation due to digital signal degradation

A. Barriga, J. Juan-Chico, M. Bellido, 1997 .

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview

Tommaso Addabbo, Erica Tena-Sánchez, Antonio J. Acosta, 2017, Int. J. Circuit Theory Appl..

Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

Erica Tena-Sánchez, Piedad Brox Jiménez, Iluminada Baturone, 2016, Int. J. Circuit Theory Appl..

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

Raúl Jiménez, Antonio J. Acosta, Jorge Juan-Chico, 2000, PATMOS.

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications

Diego Vázquez, Adoración Rueda, Ricardo Doldán, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

A switching noise vision of the optimization techniques for low-power synthesis

Javier Castro-Ramirez, Manuel Valencia-Barrero, Pilar Parra Fernández, 2007, 2007 18th European Conference on Circuit Theory and Design.

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits

Erica Tena-Sánchez, Antonio J. Acosta, Javier Castro-Ramirez, 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Analysis of Metastable Operation in a CMOS Dynamic D-Latch

M. Valencia, J. Juan-Chico, A. J. Acosta, 1997 .

Logical modelling of delay degradation effect in static CMOS gates

Antonio J. Acosta, José L. Huertas, Manuel Valencia, 2000 .

Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices

Juan Núñez, Antonio J. Acosta, Erica Tena-Sanchez, 2020, IEEE Transactions on Emerging Topics in Computing.