E. Kawamura

A Perfect Process Compatible 2.49 pm2 Embedded §RAM Cell y for 0.13 pm-Generation CMOS Logic LSIs

Y. Sambonsugi, Y. Tamura, T. Maruyama, 1998 .

Optimized Tri-Layer Resist Technique For Volume Production

E. Kawamura, J. Konno, K. Inayoshi, 1987, Advanced Lithography.

A novel embedded SRAM technology with 10-/spl mu/m/sup 2/ full-CMOS cells for 0.25-/spl mu/m logic devices

H. Shimizu, E. Kawamura, H. Takagi, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Optimized Tri-Layer Resist Technique For Volume Production

E. Kawamura, J. Konno, T. Takada, 1987, Advanced Lithography.