T. Sugii

发表

A Perfect Process Compatible 2.49 pm2 Embedded §RAM Cell y for 0.13 pm-Generation CMOS Logic LSIs

Y. Sambonsugi, Y. Tamura, T. Maruyama, 1998 .

Large Reduction in Standby Power Consumption Achieved with Stress-controlled SRAM Layout

Hiroshi Kudo, T. Sugii, Kenji Ishikawa, 2006 .

High-performance bulk CMOS technology for 65/45 nm nodes

T. Sugii, 2006 .

A Direct Tunneling Memory (DTM) utilizing novel floating gate structure

T. Sugii, N. Yokoyama, N. Horiguchi, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Batteryless sensorless bicycle speed recorder with hub dynamo and STT-MRAM

A. Tanaka, T. Douseki, M. Yoshimoto, 2015, 2015 IEEE SENSORS.

Modeling reverse short channel and narrow width effects in small size MOSFET's for circuit simulation

Chenming Hu, T. Sugii, Yuhua Cheng, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

High-Speed SOI Bipolar Transistors Using Bonding and Thinning Techniques

Tatsuya Yamazaki, Takashi Ito, T. Sugii, 1993 .

Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS

E. Yoshida, T. Sugii, M. Kojima, 2006, 2006 International Electron Devices Meeting.

A high performance 50 nm PMOSFET using decaborane (B/sub 10/H/sub 14/) ion implantation and 2-step activation annealing process

T. Sugii, T. Tanaka, Y. Momiyama, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

T. Miyashita, T. Sugii, S. Satoh, 2007, 2007 IEEE International Electron Devices Meeting.

Indium tilted channel implantation technology for 60 nm nMOSFET

T. Sugii, S. Yamaguchi, Y. Momiyama, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.

Comprehensive design methodology of dopant profile to suppress gate-LER-induced threshold voltage variability in 20nm NMOSFETs

W. Fichtner, T. Sugii, S. Satoh, 2006, 2009 Symposium on VLSI Technology.

Analytical threshold voltage model for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs

T. Sugii, Y. Tosaka, T. Sugii, 1995, 1995 IEEE International SOI Conference Proceedings.

Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET's

T. Sugii, T. Sugii, Kunihiro Suzuki, 1995 .

21 psec switching 0.1 /spl mu/m-CMOS at room temperature using high performance Co salicide process

T. Yamazaki, T. Sugii, T. Fukano, 1993, Proceedings of IEEE International Electron Devices Meeting.

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

T. Miyashita, Naoyoshi Tamura, Masataka Kase, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Experimental and simulation study on sub-50 nm CMOS design

N. Horiguchi, T. Sugii, T. Yamamoto, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's

T. Sugii, K. Suzuki, Y. Tosaka, 1994, IEEE Electron Device Letters.

Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond

T. Suzuki, T. Sugii, H. Kitada, 2008, 2008 International Interconnect Technology Conference.

A 185 GHz f/sub max/ SOI DTMOS with a new metallic overlay-gate for low-power RF applications

T. Hirose, T. Sugii, Y. Watanabe, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Impact of cosmic ray neutron induced soft errors on advanced submicron CMOS circuits

T. Sugii, S. Satoh, H. Ehara, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

T. Sugii, T. Tanaka, K. Suzuki, 1994, IEEE Electron Device Letters.

Copper Wiring Encapsulation with Ultra-thin Barriers to Enhance Wiring and Dielectric Reliabilities for 32-nm Nodes and Beyond

T. Sugii, H. Kitada, N. Ohtsuka, 2007, 2007 IEEE International Electron Devices Meeting.

MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

T. Sugii, S. Satoh, R. Tanabe, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A notched metal gate MOSFET for sub-0.1 /spl mu/m operation

Y. Sambonsugi, T. Sugii, T. Yamamoto, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Analytical threshold voltage model for short channel double-gate SOI MOSFETs

T. Sugii, Yoshiharu Tosaka, Y. Tosaka, 1996 .

Top-pinned perpendicular MTJ structure with a counter bias magnetic field layer for suppressing a stray-field in highly scalable STT-MRAM

M. Aoki, T. Sugii, T. Takenaga, 2013, 2013 Symposium on VLSI Technology.

Ultra-low contact resistance for deca-nm MOSFETs by laser annealing

T. Sugii, T. Yamamoto, K. Goto, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A novel MTJ for STT-MRAM with a dummy free layer and dual tunnel junctions

M. Aoki, T. Sugii, T. Takenaga, 2012, 2012 International Electron Devices Meeting.

Area dependence of thermal stability factor in perpendicular STT-MRAM analyzed by bi-directional data flipping model

M. Aoki, T. Sugii, Y. Iba, 2014, 2014 IEEE International Electron Devices Meeting.

A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications

Y. Sambonsugi, K. Suzuki, N. Horiguchi, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

T. Miyashita, Masaki Yamabe, Tetsu Tanaka, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application

Y. Sambonsugi, K. Suzuki, N. Horiguchi, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

A study of ultra shallow junction and tilted channel implantation for high performance 0.1 /spl mu/m pMOSFETs

T. Sugii, T. Tanaka, K. Goto, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Self-aligned control of threshold voltages in sub-0.2-/spl mu/m MOSFETs

T. Sugii, H. Kurata, 1998 .

High-speed epitaxial base transistors on bonded SOI

Tatsuya Yamazaki, Takashi Ito, T. Sugii, 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.

Reliability study of magnetic tunnel junction with naturally oxidized MgO barrier

T. Sugii, C. Yoshida, T. Sugii, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

beta -SiC/Si heterojunction bipolar transistors with high current gain

T. Sugii, M. Maeda, T. Sugii, 1988, IEEE Electron Device Letters.

High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

Masataka Kase, T. Sugii, Sergey Pidin, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

Naoto Horiguchi, Naoyoshi Tamura, Takayuki Ohba, 2003, IEEE International Electron Devices Meeting 2003.

V/sub th/ fluctuation induced by statistical variation of pocket dopant profile

Tetsu Tanaka, T. Sugii, Tatsuya Usuki, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Analytical threshold voltage model for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs

T. Sugii, Y. Tosaka, T. Sugii, 1996 .

Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation

T. Sugii, Y. Morisaki, S. Pidin, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform

T. Sugii, H. Matsuyama, S. Satoh, 2007, 2007 IEEE Symposium on VLSI Technology.

A Thin-Base Lateral Bipolar Transistor Fabricated on Bonded SOI

Takashi Ito, T. Sugii, T. Fukano, 1991, 1991 Symposium on VLSI Technology.

Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS) under ultra-low supply voltage

T. Sugii, T. Tanaka, Y. Momiyama, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Drive current enhancement by ideal junction profile using laser thermal process

T. Sugii, T. Yamamoto, K. Goto, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).