M. Anis

CAD for dual-V/sub th/ CMOS circuits

M. Anis, 2003, 2003 46th Midwest Symposium on Circuits and Systems.

Power design challenges in deep-submicron technology

M. Anis, Y. Massoud, 2003, 2003 46th Midwest Symposium on Circuits and Systems.

Comparative analysis of process variation impact on flip-flops soft error rate

M. Elmasry, M. Anis, Hassan Mostafa, 2009, 2009 1st Asia Symposium on Quality Electronic Design.

The impact of timing yield improvement under process variation on flip-flops soft error rate

M. Elmasry, M. Anis, Hassan Mostafa, 2009, 2009 1st Asia Symposium on Quality Electronic Design.

Area/yield trade-offs in scaled CMOS SRAM cell

M. Anis, V. Gupta, 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias

M. Elmasry, M. Anis, H. Mostafa, 2012, IEEE Transactions on Semiconductor Manufacturing.