Xiaokuo Yang

Low-power digital latch circuit using magnetic logic device

Li Cai, Mingliang Zhang, Tao Qin, 2015 .

Design of NAND/NOR Logic Gate Clocked by Voltage-generated Stress

Cheng Li, Bo Wei, Xiaokuo Yang, 2019 .

Total Ionizing Dose Hardening of 45 nm FD-SOI MOSFETs Using Body-Tie Biasing

Cheng Li, Xiaokuo Yang, Xiaoqiang Liu, 2019, IEEE Access.

Reliability analysis of magnetic logic interconnect wire subjected to magnet edge imperfections

Bin Zhang, Jie Xu, Wei-Wei Li, 2018 .

Error correcting circuit design with carbon nanotube field effect transistors

Li Cai, Xiaokuo Yang, Xiaoqiang Liu, 2018 .

Proposal of Global Strain Clocking Scheme for Majority Logic Gate

Bo Wei, Xiaokuo Yang, Huanqing Cui, 2020, IEEE Access.