J. Maiz

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

J. Tschanz, T. Karnik, P. Hazucha, 2003, IEEE International Electron Devices Meeting 2003.

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

Changhong Dai, J. Maiz, S. Hareland, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

S. Narendra, V. De, K. Soumyanath, 2004, IEEE Journal of Solid-State Circuits.

Characterization of multi-bit soft error events in advanced SRAMs

J. Maiz, S. Hareland, P. Armstrong, 2003, IEEE International Electron Devices Meeting 2003.

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

J. Jopling, C. Prasad, T. Ghani, 2009, 2009 IEEE International Reliability Physics Symposium.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

J. Jopling, M. Agostinelli, C. Prasad, 2008, 2008 IEEE International Reliability Physics Symposium.