S. Hareland

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

J. Tschanz, T. Karnik, P. Hazucha, 2003, IEEE International Electron Devices Meeting 2003.

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

Changhong Dai, J. Maiz, S. Hareland, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Methods for reducing soft errors in deep submicron integrated circuits

S. Hareland, K. X. Zhang, B. Senyk, 1998, 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105).

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

S. Hareland, J. Kavalieros, B. Doyle, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Characterization of multi-bit soft error events in advanced SRAMs

J. Maiz, S. Hareland, P. Armstrong, 2003, IEEE International Electron Devices Meeting 2003.

Silicon nano-transistors and breaking the 10 nm physical gate length barrier

S. Datta, S. Hareland, J. Kavalieros, 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).