H. Vaidya

A merged 2.5 V and 3.3 V 0.25-/spl mu/m CMOS technology for ASICs

S. Kuehne, R. Ashton, D. Shuttleworth, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress

A. Ghetti, H. Vaidya, W.Y.C. Lai, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A highly manufacturable corner rounding solution for 0.18 /spl mu/m shallow trench isolation

H. Vaidya, W.Y.C. Lai, M.R. Pinto, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Is surface potential measurement (SPM) a useful charging damage measurement method?

J. T. Clemens, C.-T. Liu, H. Vaidya, 1998, 1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).

Field dependent critical trap density for thin gate oxide breakdown

J. T. Clemens, J. F. Miner, C. T. Liu, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

Relationship between plasma damage, SILC and gate-oxide reliability

J. T. Clemens, J. F. Miner, C.-T. Liu, 1999, 1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395).