R. Kies

发表

Accelerated dielectric breakdown and wear out standard testing methods and structures for reliability evaluation of thin oxides

Constantin Papadas, Gerard Ghibaudo, G. Pananakakis, 1999 .

Reliability of ultra-thin buried oxides for multi-VT FDSOI technology

X. Garros, A. Toffoli, G. Reimbold, 2014 .

Engineering of the nitride charge trapping layer for non-volatile memory

G. Molas, E. Nowak, C. Licitra, 2010, 2010 27th International Conference on Microelectronics Proceedings.

Highly automated sequence for Phase Change Memory test structure characterization

G. Reimbold, B. DeSalvo, J. Cluzel, 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

G. Ghibaudo, D. Lafond, S. Deleonibus, 2011, 2011 International Electron Devices Meeting.

Temperature dependence of the Fowler–Nordheim current in metal‐oxide‐degenerate semiconductor structures

Constantin Papadas, Gerard Ghibaudo, G. Pananakakis, 1995 .

New insight on the charge trapping mechanisms of SiN-based memory by atomistic simulations and electrical modeling

G. Reimbold, D. Lafond, E. Vianello, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

X. Garros, J. Mazurier, O. Faynot, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

F. Andrieu, B. Previtali, S. Barraud, 2020, 2020 IEEE Symposium on VLSI Technology.

Reversibility of charge trapping and SILC creation in thin oxides after stress/anneal cycling

Jean Brini, Gerard Ghibaudo, G. Pananakakis, 1998 .

FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)

O. Faynot, P. Batude, S. Cristoloveanu, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

28nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D Sequential Integration: yield and reliability analysis

X. Garros, O. Rozeau, G. Ghibaudo, 2020, 2020 IEEE Symposium on VLSI Technology.

Generalized trapping kinetic model for the oxide degradation after Fowler–Nordheim uniform gate stress

Constantin Papadas, Gerard Ghibaudo, G. Pananakakis, 1997 .

Lowering the Reset Current and Power Consumption of Phase-Change Memories with Carbon-Doped Ge2Sb2Te5

G. Reimbold, P. Zuliani, G. Pananakakis, 2012, 2012 4th IEEE International Memory Workshop.

All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors

X. Garros, G. Ghibaudo, D. Bosch, 2020, 2020 IEEE Symposium on VLSI Technology.

Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

F. Andrieu, T. Ernst, S. Deleonibus, 2008, 2008 Symposium on VLSI Technology.