Motoki Amagasaki

发表

A power-gatable reconfigurable logic chip with FeRAM cells

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, 2012 International Conference on Field-Programmable Technology.

Low-Cost Image Search System on Off-Line Situation

Masahiro Iida, Motoki Amagasaki, Mery Diana, 2020, Electronics.

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

A novel states recovery technique for the TMR softcore processor

Tomoyuki Ishida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2009, 2009 International Conference on Field Programmable Logic and Applications.

A novel soft error tolerant FPGA architecture

Yuji Nakamura, Masahiro Iida, Motoki Amagasaki, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A novel three-dimensional FPGA architecture with high-speed serial communication links

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

hCODE: An open-source platform for FPGA accelerators

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

A Novel Local Interconnect Architecture for Variable Grain Logic Cell

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2009, ARC.

A case study of evaluation technique for soft error tolerance on SRAM-based FPGAs

Motoki Amagasaki, Toshinori Sueyoshi, Morihiro Kuga, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

A Microcode-based Control Unit for Deep Learning Processors

Motoki Amagasaki, Qian Zhao, Takaichi Yoshida, 2020, 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

A robust reconfigurable logic device based on less configuration memory logic cell

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2010, 2010 International Conference on Field-Programmable Technology.

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Blokus Duo engine on a Zynq

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

High-level Synthesis based on Parallel Design Patterns using a Functional Language

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, HEART.

Relationship between Recognition Accuracy and Numerical Precision in Convolutional Neural Network Models

Masahiro Iida, Motoki Amagasaki, Yasuhiro Nakahara, 2020, IEICE Trans. Inf. Syst..

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, 2010, 2010 International Conference on Field Programmable Logic and Applications.

A novel physical defects recovery technique for FPGA-IP cores

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2012, IEICE Trans. Inf. Syst..

COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2010, 2010 International Conference on Field Programmable Logic and Applications.

A SLM-based overlay architecture for fine-grained virtual FPGA

Theingi Myint, Masahiro Iida, Motoki Amagasaki, 2019, IEICE Electron. Express.

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, 2011, IEICE Trans. Electron..

A Study of Heterogeneous Computing Design Method based on Virtualization Technology

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, CARN.

Improving the soft-error tolerability of a soft-core processor on an FPGA using triple modular redundancy and partial reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2011 .

A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application : Guide to the Technical Report and Template

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2009 .

Foreword: Special section on VLSI design and CAD algorithms

Yuichiro Shibata, Makoto Ikeda, Hiroyuki Tomiyama, 2014 .

SLM: A Scalable Logic Module Architecture with Less Configuration Memory

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An easily testable routing architecture of FPGA

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

FPGA Structure

Yuichiro Shibata, Motoki Amagasaki, 2018, Principles and Structures of FPGAs.

An Easily Testable Routing Architecture and Prototype Chip

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, 2012, IEICE Trans. Inf. Syst..

A Design Framework for Reconfigurable IPs with VLSI CADs

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2012 .

FPGA based ASIC Emulator with High Speed Optical Serial Links

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, HEART.

Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, ICA3PP.

An automatic FPGA design and implementation framework

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2018, IEICE Trans. Inf. Syst..

A 3D FPGA Architecture to Realize Simple Die Stacking

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

An Easily Testable Routing Architecture and Efficient Test Technique

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2007, 2007 International Conference on Field-Programmable Technology.

FPGA Design Framework Combined with Commercial VLSI CAD

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, IEICE Trans. Inf. Syst..

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2010, TRETS.

A VARIABLEGRAINLOGICCELLARCHITECTUREFOR RECONFIGURABLE LOGIC CORES

Motoki Amagasaki, Toshinori Sueyoshi, Ryoichi Yamaguchi, 2007 .

A Case Study of Supervisor Processor for Dependable System

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012 .

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, IEICE Trans. Inf. Syst..

Fault detection and avoidance of FPGA in various granularities

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Parallelization of the channel width search for FPGA routing

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2011, CARN.

A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2011, IEEE Embedded Systems Letters.

An area compact soft error resident circuit for FPGA

Yuji Nakamura, Masahiro Iida, Motoki Amagasaki, 2016, 2016 International Conference on IC Design and Technology (ICICDT).

Deep Learning Framework with Arbitrary Numerical Precision

Masahiro Iida, Motoki Amagasaki, Masato Kiyama, 2019, 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

Low-cost Hardware that Accelerates Frequent Item Counting with an FPGA

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017 .

Zyndroid: An Android platform for software/hardware coprocessing

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

A prototype chip of reconfigurable logic device using variable grain logic cell architecture

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

Architecture exploration of 3D FPGA to minimize internal layer connection

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

FPGA placement based on self-organizing maps

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015 .

Three Dimensional FPGA Architecture with Fewer TSVs

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2018, IEICE Trans. Inf. Syst..

A novel reconfigurable logic device base on 3D stack technology

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, 2008, Int. J. Reconfigurable Comput..

Defect-robust FPGA architectures for intellectual property cores in system LSI

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, ICA3PP.

Simple wafer stacking 3D-FPGA architecture

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2015, IEICE Trans. Inf. Syst..

A less configuration memory reconfigurable logic device with error detect and correct circuit

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2007, ARC.

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, FPGA '13.

A development scheduling simulater for reconfiguable system

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012 .

Power-aware FPGA routing fabrics and design tools

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

Motion image compression circuit using the silicon retina as active sensor

Motoki Amagasaki, Fuminori Kobayashi, Minoru Watanabe, 2002, Proceedings of the 41st SICE Annual Conference. SICE 2002..

ARCHITECTURE OF GENERAL PURPOSE RECONFIGURABLE LOGIC CELL

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2006 .

Characteristic Similarity Using Classical CNN Model

Motoki Amagasaki, Morihiro Kuga, Mery Diana, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

A reconfigurable Java accelerator with software compatibility for embedded systems

Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, 2014, CARN.

Memory Sharing Approach for TMR Softcore Processor

Tomoyuki Ishida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2009, ARC.

A Quantized Neural Network Library for Proper Implementation of Hardware Emulation

Masahiro Iida, Motoki Amagasaki, Yasuhiro Nakahara, 2019, 2019 Seventh International Symposium on Computing and Networking Workshops (CANDARW).

Delay optimized technology mapping for Variable Grain Logic Cell

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2006 .

Evaluation of fault tolerant technique based on homogeneous FPGA architecture

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores

Masahiro Iida, Motoki Amagasaki, Toshinori Sueyoshi, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Novel SLM-Based Virtual FPGA Overlay Architecture

Theingi Myint, Masahiro Iida, Motoki Amagasaki, 2019, 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

Theorem-proving verification for asynchronous circuits

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2016 .

Three-dimensional stacking FPGA architecture using face-to-face integration

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

An FPGA design and implementation framework combined with commercial VLSI CADs

Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, 2013, 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

R-GCN Based Function Inference for Gate-level Netlist

Hiroaki Yasuda, Masahiro Iida, Motoki Amagasaki, 2020, IPSJ Trans. Syst. LSI Des. Methodol..

An error detect and correct circuit based fault-tolerant reconfigurable logic device (リコンフィギャラブルシステム)

Masahiro Iida, Motoki Amagasaki, Yoshihiro Ichinomiya, 2010 .

Automation of Domain-specific FPGA-IP Generation and Test

Motoki Amagasaki, Morihiro Kuga, Qian Zhao, 2021, HEART.

Development of Quantized DNN Library for Exact Hardware Emulation pdf

Motoki Amagasaki, Masato Kiyama, Masahiro Iida, 2021, ArXiv.