J. Tschanz

发表

Static pulsed bus for on-chip interconnects

M. Khellah, J. Tschanz, Y. Ye, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

J. Tschanz, T. Karnik, P. Hazucha, 2003, IEEE International Electron Devices Meeting 2003.

A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor

M. Khellah, J. Tschanz, Y. Ye, 2007, IEEE Journal of Solid-State Circuits.

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

Vivek De, J. Tschanz, S. Narendra, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

J. Tschanz, S. Narendra, V. De, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS

M. Khellah, J. Tschanz, V. De, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

AQUIS: A PC-based air quality and permit information system

J. Tschanz, C. C. Huber, A. E. Smith, 1992 .

QA procedures and emissions from nonstandard sources in AQUIS, a PC-based emission inventory and air permit manager

J. Tschanz, A. E. Smith, M. Monarch, 1996 .

Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

J. Tschanz, Liqiong Wei, Yibin Ye, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Development and deployment of AQUIS: A PC-based emission inventory calculator and air information management system

J. Tschanz, P. Narducci, A. E. Smith, 1995 .

AQUIS: A PC-based source information manager

J. Tschanz, C. C. Huber, A. E. Smith, 1993 .

Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances

J. Tschanz, V. De, K. Roy, 2011, IEEE Transactions on Electron Devices.

A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques

J. Tschanz, Y. Ye, S. Narendra, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

J. Tschanz, S. Narendra, R. Krishnamurthy, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..