T. H. Bao

The Complementary FET (CFET) for CMOS scaling beyond N3

G. Bouche, J. Ryckaert, D. Mocuta, 2018, 2018 IEEE Symposium on VLSI Technology.

Vertical GAAFETs for the Ultimate CMOS Scaling

Diederik Verkest, Anabela Veloso, Praveen Raghavan, 2015, IEEE Transactions on Electron Devices.

ZipStream: Improving dependability in dynamic partial reconfiguration

Paolo Prinetto, Pascal Trotta, Stefano Di Carlo, 2013, 2013 8th IEEE Design and Test Symposium.

Vertical nanowire FET integration and device aspects

B. T. Chan, Z. Tao, E. Rosseel, 2016 .

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

J. Swerts, A. Spessot, D. Yakimets, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM

Diederik Verkest, Piet Wambacq, Julien Ryckaert, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

SRAM designs for 5nm node and beyond: Opportunities and challenges

Diederik Verkest, Julien Ryckaert, Trong Huynh Bao, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).