Kunhyuk Kang

发表

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

Kaushik Roy, Kunhyuk Kang, Haldun Kufluoglu, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2006, Proceedings of the Design Automation & Test in Europe Conference.

ESTIMATION OFNBTIDEGRADATION USINGIDDQMEASUREMENT

Kunhyuk Kang, 2007 .

Estimation of NBTI Degradation using IDDQ Measurement

Kunhyuk Kang, M.A. Alam, K. Roy, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ

Kaushik Roy, Kunhyuk Kang, Muhammad Ashraful Alam, 2007, 2007 IEEE International Test Conference.

Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching

Kaushik Roy, Florentin Dartu, Kunhyuk Kang, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE International Conference on Test, 2005..

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications

Kaushik Roy, Jing Li, Kunhyuk Kang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Device-Aware Yield-Centric Dual-$V_{t}$ Design Under Parameter Variations in Nanoscale Technologies

Kaushik Roy, Amit Agarwal, Swarup Bhunia, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop

Kaushik Roy, Kunhyuk Kang, Keejong Kim, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling

Kaushik Roy, Jongsun Park, Ik Joon Chang, 2010, IET Circuits Devices Syst..

Analysis and design of nano-scale VLSI circuits considering the spatial and temporal reliability degradation

Kunhyuk Kang, 2007 .

Effectiveness of low power dual-V/sub t/ designs in nano-scale technologies under process parameter variations

Kaushik Roy, Amit Agarwal, Swarup Bhunia, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations

Kaushik Roy, Amit Agarwal, Kunhyuk Kang, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

High Performance and Low Power Electronics on Flexible Substrate

Kaushik Roy, Jing Li, Aditya Bansal, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling

Kaushik Roy, Chris H. Kim, Saibal Mukhopadhyay, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2006, TODE.

Reliability Implications of NBTI in Digital Integrated Circuits

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2013 .

Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI

Kaushik Roy, Kunhyuk Kang, Haldun Kufluoglu, 2006, 2006 International Conference on Computer Design.

Statistical timing analysis using levelized covariance propagation

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2005, Design, Automation and Test in Europe.

Reliability Implications of Bias-Temperature Instability in Digital ICs

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2009, IEEE Design & Test of Computers.

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement

Kaushik Roy, Kunhyuk Kang, Muhammad Ashraful Alam, 2007, 2007 44th ACM/IEEE Design Automation Conference.