Q. Yu

A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator

José B. Silva, S. Ho, P. Riehl, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

Gabriele Manganaro, Phil Brown, Janet Brunsilius, 2017, IEEE Journal of Solid-State Circuits.

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

Qicheng Yu, B.W. Garlepp, M.H. Perrott, 2006, IEEE Journal of Solid-State Circuits.

A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

Qicheng Yu, Ning Zhu, Gerry Taylor, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).