Bipin Rajendran

发表

Efficient and Robust Spiking Neural Circuit for Navigation Inspired by Echolocating Bats

Bipin Rajendran, Pulkit Tandon, Yash H. Malviya, 2016, NIPS.

A circuit model for a Si-based biomimetic synaptic time-keeping device

Udayan Ganguly, Bipin Rajendran, Vaibhav Ostwal, 2015, 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Acceleration of Convolutional Networks Using Nanoscale Memristive Devices

Bipin Rajendran, Shruti R. Kulkarni, Anakha V. Babu, 2018, EANN.

Stochastic learning in deep neural networks based on nanoscale PCMO device characteristics

Bipin Rajendran, Udayan Ganguly, Anakha V. Babu, 2018, Neurocomputing.

Training Multilayer Spiking Neural Networks using NormAD based Spatio-Temporal Error Backpropagation pdf

Bipin Rajendran, Navin Anwani, 2020, Neurocomputing.

Adversarial Training for Probabilistic Spiking Neural Networks

Alireza Bagheri, Osvaldo Simeone, Bipin Rajendran, 2018, 2018 IEEE 19th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC).

An efficient synaptic architecture for artificial neural networks

Yusuf Leblebici, Evangelos Eleftheriou, S. R. Nandakumar, 2017, 2017 17th Non-Volatile Memory Technology Symposium (NVMTS).

Delayed Guidance: A Teaching-Learning Strategy to Develop Ill-Structured Problem Solving Skills in Engineering

Sahana Murthy, Aditi Kothiyal, Bipin Rajendran, 2015, 2015 International Conference on Learning and Teaching in Computing and Engineering.

Stochastic deep learning in memristive networks

Bipin Rajendran, Anakha V. Babu, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Low-Power Neuromorphic Hardware for Signal Processing Applications: A review of architectural and system-level design approaches

Narayan Srinivasa, Evangelos Eleftheriou, Abu Sebastian, 2019, IEEE Signal Processing Magazine.

Memristive devices for deep learning applications

Damien Querlioz, Abu Sebastian, Bipin Rajendran, 2020 .

Reducing read latency of phase change memory via early read and Turbo Read

Moinuddin K. Qureshi, Chia-Chen Chou, Bipin Rajendran, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Live demonstration: Spiking neural circuit based navigation inspired by C. elegans thermotaxis

S. R. Nandakumar, Bipin Rajendran, Pritesh Shah, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Neuromorphic computing with multi-memristive synapses

Yusuf Leblebici, Thomas P. Parnell, Evangelos Eleftheriou, 2017, Nature Communications.

Building Brain-Inspired Computing Systems: Examining the Role of Nanoscale Devices

Bipin Rajendran, Shruti R. Kulkarni, Anakha V. Babu, 2018, IEEE Nanotechnology Magazine.

NormAD - Normalized Approximate Descent based supervised learning rule for spiking neurons

Bipin Rajendran, Navin Anwani, 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

Spiking neural networks — Algorithms, hardware implementations and applications

Bipin Rajendran, Shruti R. Kulkarni, Anakha V. Babu, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Spiking neural networks for handwritten digit recognition - Supervised learning and network optimization

Bipin Rajendran, Shruti R. Kulkarni, B. Rajendran, 2018, Neural Networks.

Live Demonstration: Image Classification Using Bio-inspired Spiking Neural Networks

Bipin Rajendran, Shruti R. Kulkarni, John M. Alexiades, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Analog memristive time dependent learning using discrete nanoscale RRAM devices

Bipin Rajendran, Aniket Singha, Bhaskaran Muralidharan, 2014, 2014 International Joint Conference on Neural Networks (IJCNN).

Scalable Digital CMOS Architecture for Spike Based Supervised Learning

Bipin Rajendran, Shruti R. Kulkarni, 2015, EANN.

Arithmetic computing via rate coding in neural circuits with spike-triggered adaptive synapses

Bipin Rajendran, Sushrut Thorat, 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

Characterization and Modeling

Bipin Rajendran, B. Rajendran, 2017 .

Timing analysis of tree-like RLC circuits

Chittaranjan A. Mandal, Abhishek Das, P. P. Chakrabarti, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A neural circuit for navigation inspired by C. elegans Chemotaxis pdf

Shibani Santurkar, Bipin Rajendran, B. Rajendran, 2014, arXiv.org.

Increasing reconfigurability with memristive interconnects

Simha Sethumadhavan, Steven M. Nowick, Bipin Rajendran, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Sub-threshold CMOS Spiking Neuron Circuit Design for Navigation Inspired by C. elegans Chemotaxis pdf

Shibani Santurkar, Bipin Rajendran, 2014, ArXiv.

Self-consistent power/performance/reliability analysis for copper interconnects

Pawan Kapur, Bipin Rajendran, Krishna Saraswat, 2004, SLIP '04.

Phase Change Memory: From Devices to Systems

Sudhanva Gurumurthi, Moinuddin K. Qureshi, Bipin Rajendran, 2011, Phase Change Memory.

Memristive devices as computational memory

Damien Querlioz, Abu Sebastian, Bipin Rajendran, 2020 .

Efficient scrub mechanisms for error-prone emerging memories

Vijayalakshmi Srinivasan, Rajeev Balasubramonian, Kshitij Sudan, 2012, IEEE International Symposium on High-Performance Comp Architecture.

Analytics for A Controlled Experiment to Determine Optimal Thermal Insulation for Building Envelopes

Monika Jain, Bipin Rajendran, Gagan Deep Singh, 2015, Building Simulation Conference Proceedings.

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays

Shihui Yin, Jae-Sun Seo, Bipin Rajendran, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Phase Change Memory

H.-S. Philip Wong, Simone Raoux, Mehdi Asheghi, 2010, Proceedings of the IEEE.

Training Probabilistic Spiking Neural Networks with First- To-Spike Decoding

Alireza Bagheri, Osvaldo Simeone, Bipin Rajendran, 2017, 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

Yong Liu, Bernard Brezzo, Daniel J. Friedman, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Embedded tutorial - Can silicon machines match the efficiency of the human brain?

Bipin Rajendran, B. Rajendran, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Learning and real-time classification of hand-written digits with spiking neural networks

Bipin Rajendran, Shruti R. Kulkarni, John M. Alexiades, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

C. elegans chemotaxis inspired neuromorphic circuit for contour tracking and obstacle avoidance

Shibani Santurkar, Bipin Rajendran, 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

Impact of conductance drift on multi-PCM synaptic architectures

Yusuf Leblebici, Evangelos Eleftheriou, S. R. Nandakumar, 2018, 2018 Non-Volatile Memory Technology Symposium (NVMTS).

Building Next-Generation AI systems: Co-Optimization of Algorithms, Architectures, and Nanoscale Memristive Devices

Evangelos Eleftheriou, Abu Sebastian, Bipin Rajendran, 2019, 2019 IEEE 11th International Memory Workshop (IMW).

Learning First-to-Spike Policies for Neuromorphic Control Using Policy Gradients

Osvaldo Simeone, Bipin Rajendran, Bleema Rosenfeld, 2018, 2019 IEEE 20th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC).

Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC

Albert K. Henning, Bipin Rajendran, Zvi Or-Bach, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Mixed-precision training of deep neural networks using computational memory pdf

Evangelos Eleftheriou, S. R. Nandakumar, Irem Boybat, 2017, ArXiv.

Role of resistive memory devices in brain-inspired computing

Damien Querlioz, Abu Sebastian, Bipin Rajendran, 2020 .

Mixed-precision architecture based on computational memory for training deep neural networks

Evangelos Eleftheriou, S. R. Nandakumar, Irem Boybat, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Accurate deep neural network inference using computational phase-change memory

Evangelos Eleftheriou, S. R. Nandakumar, Irem Boybat, 2019, Nature Communications.

Verilog-A compact model for a novel Cu/SiO2/W quantum memristor

S. R. Nandakumar, Bipin Rajendran, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Phase-Change Memory Models for Deep Learning Training and Inference

Irem Boybat, Manuel Le Gallo, Abu Sebastian, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Memristive devices for spiking neural networks

Damien Querlioz, Abu Sebastian, Bipin Rajendran, 2020 .

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Jae-sun Seo, Shihui Yin, Bipin Rajendran, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Guided Problem Solving and Group Programming: A Technology-Enhanced Teaching-Learning Strategy for Engineering Problem Solving

Sahana Murthy, Aditi Kothiyal, Bipin Rajendran, 2014, 2014 IEEE Sixth International Conference on Technology for Education.

Composer classification based on temporal coding in adaptive spiking neural networks

Krishnakant Saboo, Bipin Rajendran, N ChaitanyaPrasad, 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

Fast On-Device Adaptation for Spiking Neural Networks Via Online-Within-Online Meta-Learning

Osvaldo Simeone, Bipin Rajendran, Bleema Rosenfeld, 2021, 2021 IEEE Data Science and Learning Workshop (DSLW).

Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks

Jae-sun Seo, Wangxin He, Bipin Rajendran, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Spiking Generative Adversarial Networks With a Neural Network Discriminator: Local Training, Bayesian Models, and Continual Meta-Learning pdf

Osvaldo Simeone, Bipin Rajendran, Bleema Rosenfeld, 2021, IEEE Transactions on Computers.

CMOS transistor processing compatible with monolithic 3-D integration

Roger Fabian W. Pease, Bipin Rajendran, R. S. Shenoy, 2005 .

Lamellar crystallization of silicon for 3-dimensional integration

Piero Pianetta, Roger Fabian W. Pease, Bipin Rajendran, 2007 .

A 250 mV Cu/SiO2/W Memristor with Half-Integer Quantum Conductance States.

Catherine Dubourdieu, Bipin Rajendran, B. Rajendran, 2016, Nano letters.

Handling PCM Resistance Drift with Device , Circuit , Architecture , and System Solutions

Rajeev Balasubramonian, Kshitij Sudan, Manu Awasthi, .

Integrated on-chip inductors with electroplated magnetic yokes (invited)

Kenneth L. Shepard, Bucknell C. Webb, William J. Gallagher, 2012 .

Nano-graphoepitaxy of semiconductors for 3D integration

Qiangfei Xia, Roger Fabian W. Pease, Bipin Rajendran, 2007 .

Silicon nanowires for sequence-specific DNA sensing: device fabrication and simulation

R. Stanley Williams, Bipin Rajendran, Theodore I. Kamins, 2005 .