K. Vaidyanathan

Ultra-high density board technology for sub-100 /spl mu/m pitch nano-wafer level packaging

Fuhan Liu, Madhavan Swaminathan, Venky Sundaram, 2003, Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003).

Development of 3D stack package using silicon interposer for high power application

N. Khan, A.G.K. Viswanath, V.P. Ganesh, 2006, 56th Electronic Components and Technology Conference 2006.

Fluidic Interconnects in Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules

D. Pinjala, N. Khan, K. Vaidyanathan, 2008, 2008 10th Electronics Packaging Technology Conference.

Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

K. Vaidyanathan, S.K.W. Seah, C. Selvanayagam, 2008, 2008 58th Electronic Components and Technology Conference.

Copper interconnections for high performance and fine pitch flip chip digital applications and ultra-miniaturized RF module applications

P. Markondeya Raj, Sau Wee Koh, K. Vaidyanathan, 2006, 56th Electronic Components and Technology Conference 2006.