K. Ohyu

A new experimental method for evaluating electric field at the junctions of DRAM cell transistors and the effect of electric field strength on the retention characteristics of DRAM

Y. Mori, Y. Takeda, S. Kimura, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Direct observation of worst-bit leakage currents of DRAM

Y. Mori, K. Ohyu, M. Moniwa, 2006, IEEE Transactions on Electron Devices.

Hot-electron hardened Si-gate MOSFET utilizing F implantation

Y. Ohji, K. Ohyu, K. Mukai, 1989, IEEE Electron Device Letters.

Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's)

T. Nishida, T. Kure, K. Shimohigashi, 1992, IEEE Electron Device Letters.

Channel length and width dependence of hot-carrier hardness in fluorinated MOSFETs

Y. Ohji, K. Ohyu, Y. Nishioka, 1989, IEEE Electron Device Letters.

Advanced device process technology for 0.3 mu m self-aligned bipolar LSIs

T. Kure, K. Ohyu, T. Shiba, 1990, Proceedings on Bipolar Circuits and Technology Meeting.

Data retention time in DRAM with WSi/sub x//P/sup +/poly-Si gate NMOS cell transistors

H. Iwai, K. Ohyu, M. Moniwa, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Single silicon vacancy-oxygen complex defect and variable retention time phenomenon in dynamic random access memories

K. Ohyu, Takahide Umeda, K. Hamada, 2006 .

Lattice strain design in W/WN/poly-Si gate DRAM for improving data retention time

K. Ohyu, K. Okonogi, A. Toda, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..