Y. Yasu

发表

H. Kodama, Masaharu Nomachi, Y. Yasu, 1996 .

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

T. Hattori, Y. Yasu, T. Hoshi, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 60ns 1Mb Pseudo Static RAM with High Speed Modes

Y. Yasu, N. Tanimura, T. Shinoda, 1986, ESSCIRC '86: Twelfth European Solid-State Circuits Conference.

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution

Y. Yasu, H. Mizuno, K. Hirose, 2006, IEEE Journal of Solid-State Circuits.

/spl mu/I/O architecture for 0.13-/spl mu/m wide-voltage-range system-on-a-package (SoP) designs

H. Mizuno, Y. Yasu, K. Yanagisawa, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

In-Situ Measurement of Supply-Noise Maps with Millivolt Accuracy and Nanosecond-Order Time Resolution

Kenji Hirose, Yusuke Kanno, Y. Kondoh, 2006, VLSIC 2006.

Analysis of coherent data flow over Gigabit Ethernet

H. Kodama, Yoshiyuki Watase, Masaharu Nomachi, 1999, 1999 IEEE Conference on Real-Time Computer Applications in Nuclear Particle and Plasma Physics. 11th IEEE NPSS Real Time Conference. Conference Record (Cat. No.99EX295).

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

T. Hattori, T. Yamada, Y. Shimazaki, 2007, IEEE Journal of Solid-State Circuits.

Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology

Y. Maki, Y. Yasu, T. Ipposhi, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

Development of DAQ-Middleware

Noriaki Ando, Tetsuo Kotoku, Tomohisa Uchida, 2010 .

Dynamic voltage boost (DVB) method for improving power integrity of low-power multi-processor SoCs

H. Mizuno, Y. Yasu, Y. Kanno, 2008, 2008 IEEE Symposium on VLSI Circuits.

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor

T. Hattori, T. Yamada, Y. Shimazaki, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors

Y. Yasu, Y. Igarashi, O. Ozawa, 2007, 2007 IEEE Symposium on VLSI Circuits.

muI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP

Yusuke Kanno, Y. Yasu, Kazumasa Yanagisawa, 2004 .

A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current

Y. Yasu, H. Uchida, A. Ogishima, 1991 .