S. Yamasaki

Full-0.56 /spl mu/m pitch copper interconnects for a high performance 0.15-/spl mu/m CMOS logic device

S. Yokogawa, K. Sugai, A. Nishizawa, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Cleaning Technologies using Electrolytic Ionized Water and Analysis Technology of Fine Structures for Next Generation Device Manufacturing

K. Yamanaka, T. Imaoka, T. Futatsuki, 1997 .

Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrier

K. Yoshida, N. Kasai, K. Fujii, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Multilevel Aluminum Dual-Damascene Interconnects for Process-Step Reduction in 0.18 µm ULSIs

Y. Hayashi, H. Wakabayashi, A. Kubo, 1999 .

Native oxides on Si surfaces of deep‐submicron contact‐hole bottoms

H. Hada, Y. Teraoka, I. Nishiyama, 1995 .

A New Technique for Quantitative Analysis of Metallic Contamination inside Deep-Submicron-Diameter Holes

S. Yamasaki, N. Aoto, H. Aoki, 1996 .