André Inácio Reis

发表

Spin diode network synthesis using functional composition

Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Factored Forms for Memristive Material Implication Stateful Logic

Mayler G. A. Martins, Felipe S. Marranghello, Renato P. Ribas, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Concepção de Circuitos e Sistemas Integrados

Marcelo Lubaszewski, Renato P. Ribas, André Inácio Reis, 2001, RITA.

What about the IP of your IP?: an introduction to intellectual property law for engineers and scientists

André Inácio Reis, Roner G. Fabris, 2009, SBCCI.

Routing Resistance Influence in Loading Effect on Leakage Analysis

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2009, PATMOS.

Iterative remapping respecting timing constraints

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Transistor Sizing Analysis of Regular Fabrics

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2011, ARCS Workshops.

Scheduling Policy Costs on a JAVA Microcontroller

Luigi Carro, Leomar S. da Rosa, Flávio Rech Wagner, 2003, OTM Workshops.

Lithography analysis of via-configurable transistor-array fabrics

Renato P. Ribas, André Inácio Reis, Vinícius Dal Bem, 2012, NORCHIP 2012.

Contributions to Modeling Patent Claims When Representing Patent Knowledge

Pompeu Casanovas, André Inácio Reis, Jordi Carrabina, 2017, AICOL.

Constructive AIG optimization considering input weights

Renato P. Ribas, André Inácio Reis, Thiago Figueiro, 2011, 2011 12th International Symposium on Quality Electronic Design.

Deriving reduced transistor count circuits from AIGs

Renato P. Ribas, André Inácio Reis, Marcus Ritt, 2014, 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI).

Open Cell Library in 15nm FreePDK Technology

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2015, ISPD.

BTI, HCI and TDDB aging impact in flip-flops

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2013, Microelectron. Reliab..

Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2010, J. Low Power Electron..

Exploring independent gates in FinFET-based transistor network generation

Felipe S. Marques, Leomar S. da Rosa, Renato P. Ribas, 2014, 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI).

Contributions to the evaluation of ensembles of combinational logic gates

Marcelo Lubaszewski, Renato P. Ribas, André Inácio Reis, 2011, Microelectron. J..

Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution

André Inácio Reis, A. Reis, 2018, ISPD.

Transistor network restructuring against NBTI degradation

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2010, Microelectron. Reliab..

Constructive AIG optimization through functional composition

Renato P. Ribas, André Inácio Reis, Thiago Figueiro, 2011, ARCS Workshops.

Modeling and estimating leakage current in series-parallel CMOS networks

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2007, GLSVLSI '07.

Synthesis of threshold logic gates to nanoelectronics

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Area impact analysis of via-configurable regular fabric for digital integrated circuit design

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2011, SBCCI '11.

Enhanced Spin-Diode Synthesis Using Logic Sharing

Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, 2015, 2015 Euromicro Conference on Digital System Design.

SOP based logic synthesis for memristive IMPLY stateful logic

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2013, Microelectron. Reliab..

Efficient method to compute minimum decision chains of Boolean functions

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2011, GLSVLSI '11.

Advanced Logic Synthesis

Rolf Drechsler, André Inácio Reis, R. Drechsler, 2018 .

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2018, 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI).

A methodology to evaluate the aging impact on flip-flops performance

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Boolean factoring with multi-objective goals

Mayler G. A. Martins, Leomar S. da Rosa, Renato P. Ribas, 2010, 2010 IEEE International Conference on Computer Design.

Methodology for achieving best trade-off of area and fault masking coverage in ATMR

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2014, 2014 15th Latin American Test Workshop - LATW.

Delay model for static CMOS complex gates

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

KL-cut based digital circuit remapping

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2012, NORCHIP 2012.

Threshold logic synthesis based on cut pruning

Alan Mishchenko, Renato P. Ribas, André Inácio Reis, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Technology Mapping for Circuits with Simple Cells

André Inácio Reis, Jordi Carrabina, Jody Maick Matos, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Impact and optimization of lithography-aware regular layout in digital circuit design

Paulo F. Butzen, Felipe S. Marranghello, Renato P. Ribas, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Comparing Transistor-Level Implementations of 4-Input Logic Functions

Renato P. Ribas, André Inácio Reis, Felipe Ribeiro Schneider, 2002, IWLS.

DAG based library-free technology mapping

Sachin S. Sapatnekar, Felipe S. Marques, Leomar S. da Rosa, 2007, GLSVLSI '07.

CMOS inverter delay model based on DC transfer curve for slow input

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2013, International Symposium on Quality Electronic Design (ISQED).

Efficient test circuit to qualify logic cells

Marcelo Lubaszewski, Renato P. Ribas, André Inácio Reis, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Exploring the use of approximate TMR to mask transient faults in logic with low area overhead

Mayler G. A. Martins, André Inácio Reis, Fernanda Gusmão de Lima Kastensmidt, 2015, Microelectron. Reliab..

Graph-Based Transistor Network Generation Method for Supergate Design

Leomar S. da Rosa, Renato P. Ribas, André Inácio Reis, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Improvements on the detection of false paths by using unateness and satisfiability

Felipe S. Marques, Renato P. Ribas, André Inácio Reis, 2010, SBCCI '10.

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

Leomar S. da Rosa, Renato P. Ribas, André Inácio Reis, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Design of CMOS logic gates with enhanced robustness against aging degradation

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2012, Microelectron. Reliab..

Performance and functional test of flip-flops using ring oscillator structure

André Ivanov, Renato P. Ribas, André Inácio Reis, 2011, 2011 IEEE 6th International Design and Test Workshop (IDT).

Advanced technology mapping for standard-cell generators

André Inácio Reis, Vinícius P. Correia, 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

Optimization on cell-library design for digital Application Specific Printed Electronics Circuits

André Inácio Reis, Jordi Carrabina, Mohammad Mashayekhi, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Power consumption analysis in static CMOS gates

Renato P. Ribas, André Inácio Reis, Kim A. Escobar, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Fast buffer delay estimation considering time-dependent dielectric breakdown

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Fast disjoint transistor networks from BDDs

Sachin S. Sapatnekar, Felipe S. Marques, Leomar S. da Rosa, 2006, SBCCI '06.

Efficient transistor-level design of CMOS gates

Leomar S. da Rosa, Renato P. Ribas, André Inácio Reis, 2013, GLSVLSI '13.

CMOS inverter analytical delay model considering all operating regions

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology

Renato P. Ribas, André Inácio Reis, Digeorgia N. da Silva, 2010, Microelectron. Reliab..

Binary adder circuit design using emerging MIGFET devices

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Performance evaluation of optimized transistor networks built using independent-gate FinFET

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2016, 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS).

CMOS logic gate performance variability related to transistor network arrangements

Renato P. Ribas, André Inácio Reis, Digeorgia N. da Silva, 2009, Microelectron. Reliab..

Logic synthesis for manufacturability considering regularity and lithography printability

Renato P. Ribas, André Inácio Reis, Sergio Gómez, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A comparative study of CMOS gates with minimum transistor stacks

Leomar S. da Rosa, Renato P. Ribas, André Inácio Reis, 2007, SBCCI '07.

Improving the methodology to build non-series-parallel transistor arrangements

Felipe S. Marques, Leomar S. da Rosa, Renato P. Ribas, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Compression and technology mapping of logic circuits

André Inácio Reis, Vinícius Pazutti Correia, 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design

Renato P. Ribas, André Inácio Reis, Jody Maick Matos, 2015, ISPD.

Asynchronous circuit design on reconfigurable devices

Renato P. Ribas, André Inácio Reis, R. U. R. Mocho, 2006, SBCCI '06.

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels

Davide Pandini, Fabrizio Ferrandi, Renato P. Ribas, 2011, ARCS Workshops.

Functional composition: A new paradigm for performing logic synthesis

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Unlocking Fine-Grain Parallelism for AIG Rewriting

Keshav Pingali, Alan Mishchenko, Renato P. Ribas, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Analytical logical effort formulation for minimum active area under delay constraints

Renato P. Ribas, André Inácio Reis, Vinícius Dal Bem, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Ring oscillators for functional and delay test of latches and flip-flops

André Ivanov, Renato P. Ribas, André Inácio Reis, 2011, SBCCI '11.

Switch level optimization of digital CMOS gate networks

Leomar S. da Rosa, Renato P. Ribas, André Inácio Reis, 2009, 2009 10th International Symposium on Quality Electronic Design.

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Paulo F. Butzen, Leomar S. da Rosa, Renato P. Ribas, 2010, Microelectron. J..

Transistor sizing in lithography-aware regular fabrics

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2011, SBCCI '11.

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis

Mayler G. A. Martins, Felipe S. Marranghello, Renato P. Ribas, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

A constructive approach for threshold logic circuit synthesis

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Using only redundant modules with approximate logic to reduce drastically area overhead in TMR

Mayler G. A. Martins, André Inácio Reis, Fernanda Gusmão de Lima Kastensmidt, 2015, 2015 16th Latin-American Test Symposium (LATS).

Improved logic synthesis for memristive stateful logic using multi-memristor implication

Mayler G. A. Martins, Felipe S. Marranghello, Renato P. Ribas, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Read-polarity-once Boolean functions

Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

Unified theory to build cell-level transistor networks from BDDs [logic synthesis]

Renato P. Ribas, André Inácio Reis, Felipe Ribeiro Schneider, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

A tutorial tool for switch logic

André Inácio Reis, Vinícius P. Correia, 2001, Proceedings 2001 International Conference on Microelectronic Systems Education.

Tool integration using the web-services approach

Renato P. Ribas, André Inácio Reis, Maria Lúcia Blanck Lisbôa, 2005, GLSVLSI '05.

Exact lower bound for the number of switches in series to implement a combinational logic cell

Sachin S. Sapatnekar, Renato P. Ribas, André Inácio Reis, 2005, 2005 International Conference on Computer Design.

Fast-extract with cube hashing

Robert K. Brayton, Alan Mishchenko, André Inácio Reis, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2007, PATMOS.

KARMA: A Didactic Tool for Two-Level Logic Synthesis

Renato P. Ribas, André Inácio Reis, Carlos Eduardo Klock, 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic

Renato P. Ribas, André Inácio Reis, Mário C. B. Osorio, 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

SIFU!-a didactic stuck-at fault simulator

Marcelo Lubaszewski, André Inácio Reis, Vinícius P. Correia, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

Design-oriented delay model for CMOS inverter

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2012, 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI).

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC

Felipe S. Marranghello, Renato P. Ribas, André Inácio Reis, 2017, IEEE Transactions on Emerging Topics in Computing.

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements

Felipe S. Marques, Leomar S. da Rosa, Renato P. Ribas, 2012, 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI).

A new approach to the use of satisfiability in false path detection

Sachin S. Sapatnekar, Felipe S. Marques, Renato P. Ribas, 2005, GLSVLSI '05.

Self-checking test circuits for latches and flip-flops

André Ivanov, Renato P. Ribas, André Inácio Reis, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks

Felipe S. Marques, Renato P. Ribas, André Inácio Reis, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

SwitchCraft: a framework for transistor network design

Leomar S. da Rosa, Renato P. Ribas, André Inácio Reis, 2010, SBCCI '10.

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms

Paulo F. Butzen, Leomar S. da Rosa, Renato P. Ribas, 2008, GLSVLSI '08.

Modeling Subthreshold Leakage Current in General Transistor Networks

Paulo F. Butzen, Renato P. Ribas, André Inácio Reis, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

Mayler G. A. Martins, Matheus T. Moreira, Renato P. Ribas, 2014, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems.