Payman Zarkesh-Ha

发表

Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-Systems

Ahmad Atghiaee, Nasser Masoumi, Payman Zarkesh-Ha, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The effect of power supply ramp time on SRAM PUFs

Payman Zarkesh-Ha, Abdelrahman T. Elshafiey, Joshua Trujillo, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Multi-wavelength visible light communication system design

Payman Zarkesh-Ha, Thomas D. C. Little, Hany Elgala, 2014, 2014 IEEE Globecom Workshops (GC Wkshps).

A linear digital VCO for Clock Data Recovery (CDR) applications

Payman Zarkesh-Ha, Ryan Helinski, Thomas LeBoeuf, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

CMOS approach to compressed-domain image acquisition.

Payman Zarkesh-Ha, Sanjay Krishna, Manish Bhattarai, 2017, Optics express.

Reducing energy and increasing performance with traffic optimization in many-core systems

Payman Zarkesh-Ha, Stephanie Forrest, George B. P. Bezerra, 2011, International Workshop on System Level Interconnect Prediction.

Evaluating mobile SOCs as an energy efficient DSP platform

Payman Zarkesh-Ha, Matt Briggs, P. Zarkesh-Ha, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

IC Memory Circuits

Payman Zarkesh-Ha, Charles F. Hawkins, Jaume Segura, 2013 .

Interconnect opportunities for gigascale integration

Payman Zarkesh-Ha, James D. Meindl, Jeffrey A. Davis, 2002, IBM J. Res. Dev..

5.2dB Sensitivity Enhancement in 25Gbps APD-Based Optical Receiver using Dynamic Biasing

Payman Zarkesh-Ha, Majeed M. Hayat, Robert Efroymson, 2020, 2020 Optical Fiber Communications Conference and Exhibition (OFC).

Stochastic interconnect layout sensitivity model

Payman Zarkesh-Ha, Ken Doniger, 2007, SLIP '07.

Impact of interconnect pattern density information on a 90 nm technology ASIC design flow

Payman Zarkesh-Ha, Peter Wright, Ken Doniger, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Hybrid network on chip (HNoC): local buses with a global mesh architecture

Payman Zarkesh-Ha, Stephanie Forrest, Melanie E. Moses, 2010, SLIP '10.

CMOS Circuit Layout

Payman Zarkesh-Ha, Jaume Segura, Charles Hawkins Hawkins, 2013 .

SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements

Payman Zarkesh-Ha, Steven C. Suddarth, Srikanth V. Devarapalli, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

Reconfigurable power management using novel monolithically integrated CMOS-on-PV switch

Payman Zarkesh-Ha, Jonathan West, Jim Aarestad, 2014, 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC).

Data compressive paradigm for multispectral sensing using tunable DWELL mid-infrared detectors.

Payman Zarkesh-Ha, Sanjay Krishna, Woo-Yong Jang, 2011, Optics express.

Global interconnect design in a three-dimensional system-on-a-chip

Payman Zarkesh-Ha, James D. Meindl, James W. Joyner, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Sequential Logic Gate Design and Timing

Payman Zarkesh-Ha, Charles F. Hawkins, Jaume Segura, 2013 .

Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures

Payman Zarkesh-Ha, James D. Meindl, Jeffrey A. Davis, 2000, SLIP '00.

A novel readout circuit for on-sensor multispectral classification

Payman Zarkesh-Ha, Sanjay Krishna, Majeed M. Hayat, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

CMOS Digital Integrated Circuits: A first course

Payman Zarkesh-Ha, Charles F. Hawkins, Jaume Segura, 2012 .

Intelligent bias-selection method for computational imaging on a CMOS imager

Majeed M. Hayat, Payman Zarkesh-Ha, Sanjay Krishna, 2016, 2016 IEEE Photonics Conference (IPC).

Prediction of interconnect adjacency distribution: derivation, validation, and applications

Payman Zarkesh-Ha, Peter Bendix, Ken Doniger, 2004, SLIP '04.

Power, Clock, and Global Signal Distribution

Payman Zarkesh-Ha, 2003 .

Spatio-temporal tunable pixels for multi-spectral infrared imagers

Payman Zarkesh-Ha, Sanjay Krishna, Javad Ghasemi, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Prediction of interconnect fan-out distribution using Rent's rule

Payman Zarkesh-Ha, James D. Meindl, Jeffrey A. Davis, 2000, SLIP '00.

Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model

Payman Zarkesh-Ha, Rani S. Ghaida, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

A meter-scale 600-Mb/s 2×2 imaging MIMO OOK VLC link using commercial LEDs and Si p-n photodiode array

Payman Zarkesh-Ha, Mona Mostafa Hella, Bassem Fahs, 2017, 2017 26th Wireless and Optical Communication Conference (WOCC).

Analytical Noise-Rejection Model Based on Short Channel MOSFET

Payman Zarkesh-Ha, Vinay Jain, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Predictive Model for Extreme Electromagnetic Compatibility on CMOS Inverters

Payman Zarkesh-Ha, Sameer Hemmady, Troy Powell, 2018, 2018 International Symposium on Electromagnetic Compatibility (EMC EUROPE).

Analytical Noise-Rejection Model Based on Short Channel MOSFET

Payman Zarkesh-Ha, V. Jain, 2008, ISQED 2008.

A new CMOS readout circuit approach for multispectral imaging

Payman Zarkesh-Ha, Sanjay Krishna, Javad Ghasemi, 2013, 2013 IEEE Photonics Conference.

Analysis of low-voltage mixed-signal circuits under device variations

Payman Zarkesh-Ha, 2013, 2013 IEEE Faible Tension Faible Consommation.

Prediction of interconnect pattern density distribution: derivation, validation, and applications

Payman Zarkesh-Ha, Peter Wright, Ken Doniger, 2003, SLIP '03.

Analytical noise model for avalanche ISFET sensor suitable for Next Generation Sequencing

Payman Zarkesh-Ha, Jeremy S. Edwards, Mohammad M. Uzzal, 2016, 2016 29th IEEE International System-on-Chip Conference (SOCC).

CMOS Integrated Digital Electronics: A First Course

Payman Zarkesh-Ha, Jaume Segura, Charles Hawkins Hawkins, 2013 .

A CMOS-Compatible Plenoptic Sensor Array for Smart Lighting Applications

Payman Zarkesh-Ha, Steven R. J. Brueck, Alexander Neumann, 2017 .

Behavioral modeling of drain current of an avalanche ISFET near breakdown

Payman Zarkesh-Ha, Jeremy S. Edwards, Mohammad M. Uzzal, 2016, 2016 29th IEEE International System-on-Chip Conference (SOCC).

CMOS NAND, NOR, and Transmission Gates

Payman Zarkesh-Ha, Charles F. Hawkins, Jaume Segura, 2013 .

Session details: Power Grid and Signal Integrity Analysis

Payman Zarkesh-Ha, 2002, SLIP '02.

A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects

Payman Zarkesh-Ha, Rani S. Ghaida, P. Zarkesh-Ha, 2009, J. Electron. Test..

Reconfigurable power management for monolithic CMOS-on-Photovoltaic under partial and complete shading

Payman Zarkesh-Ha, Olga Lavrova, Rakeskumar Mahto, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Avalanche ISFET: A highly sensitive pH sensor for genome sequencing

Payman Zarkesh-Ha, Paul Szauter, Jeremy S. Edwards, 2015, 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS).

A Compact model for analysis and design of on-chip power network with decoupling capacitors

Payman Zarkesh-Ha, Ken Doniger, William Loh, 2003, Proceedings 21st International Conference on Computer Design.

Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip

Payman Zarkesh-Ha, James D. Meindl, Jeffrey A. Davis, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Prediction of gate delay variation for CNFET under CNT density variation

Payman Zarkesh-Ha, Ali Arabi M. Shahi, P. Zarkesh-Ha, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Basic Logic Gate and Circuit Theory

Payman Zarkesh-Ha, Charles F. Hawkins, Jaume Segura, 2013 .

Programmable Logic - FPGAs

Payman Zarkesh-Ha, Jaume Segura, Charles Hawkins Hawkins, 2013 .

The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings

Dennis Sylvester, Payman Zarkesh-Ha, Dirk Stroobandt, 2003, SLIP.

A robust 2×2 CMOS receiver array for meter-scale point-to-point OOK VLC links

Payman Zarkesh-Ha, Mona M. Hella, Bassem Fahs, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Predicting the Tolerance of Extreme Electromagnetic Interference on MOSFETs

Payman Zarkesh-Ha, Sameer Hemmady, Troy Powell, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A novel LED/detector integrated circuit

Payman Zarkesh-Ha, 2011 .

Scavenger: An Adaptive Design Technique for Low Power ASIC/FPGA

Payman Zarkesh-Ha, Steven C. Suddarth, Vallabh Srikanth Devarapalli, 2009, 2009 International Conference on Computing, Engineering and Information.

Comparison of variations in MOSFET versus CNFET in gigascale integrated systems

Payman Zarkesh-Ha, Ali Arabi M. Shahi, Mirza Elahi, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

CMOS Circuit Design Styles

Payman Zarkesh-Ha, Charles F. Hawkins, Jaume Segura, 2013 .

Predictive Modeling for Estimating the Limits for Nonpersistent Effects in MOSFET Response Under Large Signal Gate Injection

Payman Zarkesh-Ha, Edl Schamiloglu, Sameer Hemmady, 2020, IEEE Transactions on Electromagnetic Compatibility.

An intelligent readout circuit for infrared multispectral remote sensing

Payman Zarkesh-Ha, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

Reconfigurable photovoltaic integrated with CMOS for a fault tolerant system

Payman Zarkesh-Ha, Olga Lavrova, Rakeshkumar Mahto, 2016, 2016 IEEE 43rd Photovoltaic Specialists Conference (PVSC).

Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing

Payman Zarkesh-Ha, Sanjay Krishna, Javad Ghasemi, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Impact of three-dimensional architectures on interconnects in gigascale integration

Payman Zarkesh-Ha, James D. Meindl, Jeffrey A. Davis, 2001, IEEE Trans. Very Large Scale Integr. Syst..

A robust and low power dual data rate (DDR) flip-flop using c-elements

Payman Zarkesh-Ha, Steven C. Suddarth, Srikanth V. Devarapalli, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

A highly sensitive ISFET using pH-to-current conversion for real-time DNA sequencing

Payman Zarkesh-Ha, Jeremy S. Edwards, Priyanka Rawat, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

Modeling NoC traffic locality and energy consumption with rent's communication probability distribution

Payman Zarkesh-Ha, Stephanie Forrest, George B. P. Bezerra, 2010, SLIP '10.

Logic Gate Failure Characterization for Nanoelectronic EDA Tools

Payman Zarkesh-Ha, Ali Arabi M. Shahi, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

An embedded system for face classification in infrared video using sparse representation

Miguel Figueroa, Jorge E. Pezoa, Payman Zarkesh-Ha, 2017, Optical Engineering + Applications.

Continuous time-varying biasing approach for spectrally tunable infrared detectors.

Payman Zarkesh-Ha, Sanjay Krishna, Woo-Yong Jang, 2012, Optics express.

Impact of Memristor Defects in a Neuromorphic Radionuclide Identification System

Christof Teuscher, Payman Zarkesh-Ha, Walt Woods, 2020, ISCAS.

A compact physical via blockage model

Qiang Chen, Payman Zarkesh-Ha, James D. Meindl, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

Payman Zarkesh-Ha, Edl Schamiloglu, Thomas M. Antonsen, 2021 .

Face Recognition on a Smart Image Sensor Using Local Gradients

Payman Zarkesh-Ha, Javier E. Soto, Wladimir E. Valenzuela, 2021, Sensors.

A 6-m OOK VLC Link Using CMOS-Compatible p-n Photodiode and Red LED

Payman Zarkesh-Ha, Mona M. Hella, Bassem Fahs, 2016, IEEE Photonics Technology Letters.

Design and Modeling of Blue-Enhanced and Bandwidth-Extended PN Photodiode in Standard CMOS Technology

Payman Zarkesh-Ha, Mona Mostafa Hella, Bassem Fahs, 2017, IEEE Transactions on Electron Devices.

Speed optimized large area avalanche photodetector in standard CMOS technology for visible light communication

Majeed M. Hayat, Payman Zarkesh-Ha, Mona M. Hella, 2014, IEEE SENSORS 2014 Proceedings.

Low breakdown voltage CMOS compatible p-n junction avalanche photodiode

Majeed M. Hayat, John P. R. David, Payman Zarkesh-Ha, 2014, 2014 IEEE Photonics Conference.

The CMOS Inverter

Payman Zarkesh-Ha, Charles F. Hawkins, Jaume Segura, 2013 .

Nano-scale early-design-stage prediction for crosstalk-induced power

Ahmad Atghiaee, Nasser Masoumi, Payman Zarkesh-Ha, 2010, 2010 3rd International Nanoelectronics Conference (INEC).

Breaking the buildup-time limit of sensitivity in avalanche photodiodes by dynamic biasing.

Payman Zarkesh-Ha, Majeed M Hayat, Georges El-Howayek, 2015, Optics express.