S. Mathew

A 64-state 2GHz 500Mbps 40mW Viterbi accelerator in 90nm CMOS

R. Krishnamurthy, S. Borkar, M. Anders, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS

R. Krishnamurthy, A. Agarwal, S. Borkar, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 6.5GHz 54mW 64-bit Parity-Checking Adder for 65nm Fault-Tolerant Microprocessor Execution Cores

R. Krishnamurthy, S. Borkar, M. Anders, 2007, 2007 IEEE Symposium on VLSI Circuits.

A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core

R. Krishnamurthy, S. Borkar, M. Anders, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS

S. Vangal, N. Borkar, S. Mathew, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core

R. Krishnamurthy, M. Anders, S. Mathew, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme

A. Alvandpour, S. Borkar, S. Mathew, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Advanced circuit techniques for high-performance microprocessor and low-power DSPs

R. Krishnamurthy, S. Borkar, M. Anders, 2004, Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits.