Rita Rooyackers

发表

Advanced semiconductor devices for future CMOS technologies

Cor Claeys, Daniele Chiappe, Nadine Collaert, 2015 .

Methodology for Design Optimization of SOI FinFET Grounded-Gate NMOS Devices

Mirko Scholz, Dimitri Linten, Rita Rooyackers, 2010, IEEE Transactions on Device and Materials Reliability.

Shift and ratio method revisited: extraction of the fin width in multi-gate devices

Nadine Collaert, Rita Rooyackers, K. De Meyer, 2005 .

Ultimate nano-electronics

Jerome Mitard, Rita Rooyackers, Anne Vandooren, 2015 .

Study of line-TFET analog performance comparing with other TFET and MOSFET architectures

Rita Rooyackers, Anne Vandooren, Aaron Thean, 2017 .

Material Aspects and Challenges for SOI FinFET Integration

Rita Rooyackers, Liesbeth Witters, Nadine Collaert, 2008 .

Comprehensive approach to MuGFET metrology

Rita Rooyackers, Philippe Leray, Shaunee Cheng, 2006, SPIE Advanced Lithography.

Advanced FinFET Devices for Sub-32nm Technology Nodes: Characteristics and Integration Challenges

Rita Rooyackers, Anabela Veloso, Liesbeth Witters, 2009 .

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

Vincent Wiaux, Rita Rooyackers, Staf Verhaegen, 2004 .

Design methodology for FinFET GG-NMOS ESD protecction devices

Charvaka Duvvury, Mirko Scholz, Dimitri Linten, 2008 .

Selective Epitaxy of Si/SiGe to Improve pMOS Devices by Recessed Source/Drain and/or Buried SiGe Channels

Akira Inoue, Rita Rooyackers, Denis Shamiryan, 2006 .

Multi-gate devices for the 32 nm technology node and beyond

Rita Rooyackers, Nadine Collaert, Isabelle Ferain, 2008 .

Validation of CD-SEM etching residue evaluation technique for MuGFET structures

Tatsuya Maeda, Rita Rooyackers, Kenji Watanabe, 2009, Advanced Lithography.

Suitability ofFinFETtechnology forlow-power mixed-signal applications

P. Wambacq, Rita Rooyackers, S. Decoutere, 2006 .

MuGFET observation and CD measurement by using CD-SEM

Tatsuya Maeda, Rita Rooyackers, Kenji Watanabe, 2008, SPIE Advanced Lithography.

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Temperature impact on the tunnel fet off-state current components

Cor Claeys, Rita Rooyackers, Paula Ghedini Der Agopian, 2012 .

The effect of Ga pre-deposition on Si (111) surface for InAs nanowire selective area hetero-epitaxy

Rita Rooyackers, Aaron Thean, Wilfried Vandervorst, 2018 .

Record performance InGaAs homo-junction TFET with superior SS reliability over MOSFET

Rita Rooyackers, Anne Vandooren, Aaron Thean, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Tunnel Field-Effect Transistors for Future Low-Power Nano-Electronics

Rita Rooyackers, Anne Vandooren, Guido Groeseneken, 2009 .

Spacer defined FinFET: Active area patterning of sub-20nm fins with high density

Rita Rooyackers, Denis Shamiryan, Nadine Collaert, 2007 .

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Marcelo Antonio Pavanello, Cor Claeys, Rita Rooyackers, 2008 .

Fabrication and Analysis of a Heterojunction Line Tunnel FET

Rita Rooyackers, Anne Vandooren, Aaron Thean, 2014 .

Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature

Cor Claeys, Rita Rooyackers, Eddy Simoen, 2013, IEEE Transactions on Electron Devices.

Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs

Rita Rooyackers, Anne Vandooren, Guido Groeseneken, 2013 .

Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism

Cor Claeys, Rita Rooyackers, Eddy Simoen, 2015 .

Mobility characterization in FinFETs using split C-V technique

Denis Flandre, Rita Rooyackers, Jean-Pierre Raskin, 2005 .

The impact of the Ge concentration in the source for vertical tunnel-FETs

Cor Claeys, Rita Rooyackers, Eddy Simoen, 2015 .

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

Rita Rooyackers, Nadine Collaert, Malgorzata Jurczak, 2008 .

NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics

Rita Rooyackers, Wim Deweerd, Tom Schram, 2005 .

Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs

Rita Rooyackers, Anne Vandooren, Guido Groeseneken, 2012 .

Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs

Cor Claeys, Rita Rooyackers, Eddy Simoen, 2015, IEEE Transactions on Electron Devices.

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

Emmanuel Augendre, Dimitri Linten, Rita Rooyackers, 2003 .

Part II: Investigation of Subthreshold Swing in Line Tunnel FETs Using Bias Stress Measurements

Rita Rooyackers, Eddy Simoen, Anne Vandooren, 2013, IEEE Transactions on Electron Devices.

Drain voltage dependent analytical model of tunnel field-effect transistors

Rita Rooyackers, Guido Groeseneken, Daniele Leonelli, 2011 .

Trends and Challenges in Si and Hetero-Junction Tunnel Field Effect Transistors

Cor Claeys, Rita Rooyackers, Anne Vandooren, 2011 .

Silicide Engineering to Boost Si Tunnel Transistor Drive Current

Rita Rooyackers, Anne Vandooren, Guido Groeseneken, 2011 .

Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation

Marcelo Antonio Pavanello, Rita Rooyackers, Eddy Simoen, 2007 .

Migrating from planar to FinFET for further CMOS scaling: SOI or Bulk?

Rita Rooyackers, Liesbeth Witters, C. Ortolland, 2009, ESSDERC 2009.

Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity

Emmanuel Augendre, Rita Rooyackers, E. P. Vandamme, 2000 .

The etchback approach: Enlarged process window for MuGFET gate etching

Rita Rooyackers, Nadine Collaert, Malgorzata Jurczak, 2006 .

Shallow trench isolation dimensions effects on leakage current and doping concentration of advanced p–n junction diodes

Rita Rooyackers, Eddy Simoen, Amporn Poyai, 2004 .

Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs

Denis Flandre, Cor Claeys, Rita Rooyackers, 2011 .

Polysilicon Encapsulated LOCOS for Deep Submicron CMOS Lateral Isolation

Rita Rooyackers, Ludo Deferm, Ingrid De Wolf, 1996 .