N. Aoki

发表

Process dependence of 1/f noise : For realization of high performance analog circuits

Kazuya Matsuzawa, K. Kojima, Tatsuya Ohguro, 2003 .

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

H. Mizuno, T. Morooka, K. Ohuchi, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

20nm-node planer MONOS cell technology for multi-level NAND Flash Memory

K. Narita, H. Maekawa, N. Aoki, 2006, 2009 Symposium on VLSI Technology.

Damping circuit to suppress motor terminal overvoltage and ringing in PWM inverter-fed AC motor drive systems with long motor leads

K. Satoh, N. Aoki, A. Nabae, 1998, Conference Record of 1998 IEEE Industry Applications Conference. Thirty-Third IAS Annual Meeting (Cat. No.98CH36242).

SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications

N. Aoki, T. Sato, T. Tsunashima, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications

Atsushi Sakamoto, Akihiro Nitayama, Takashi Ohsawa, 2006, 2006 IEEE International Conference on IC Design and Technology.

Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM

K. Yahashi, R. Katsumata, M. Morikado, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

Atsushi Sakamoto, Akihiro Nitayama, Takashi Ohsawa, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, 2005 IEEE International SOI Conference Proceedings.

Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Y. Toyoshima, K. Ohuchi, N. Aoki, 2006, 2006 International Electron Devices Meeting.

Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

N. Nagashima, K. Ohuchi, H. Ishiuchi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration

N. Aoki, I. Mizushima, Y. Tsunashima, 1999 .

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

H. Ishiuchi, N. Aoki, K. Ishimaru, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

K. Yahashi, N. Kusunoki, K. Ohuchi, 2006, 2006 European Solid-State Device Research Conference.

Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

Y. Toyoshima, N. Aoki, K. Ishimaru, 2007, 2007 IEEE International Electron Devices Meeting.

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Akihiro Nitayama, Takashi Ohsawa, K. Inoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Issues and optimization of millisecond anneal process for 45 nm node and beyond

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration

N. Aoki, I. Mizushima, Y. Tsunashima, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..