Warin Sootkaneung

Soft Error-Aware Leakage Reduction through Body Bias

Warin Sootkaneung, S. Howimanporn, S. Chookaew, 2017 .

Temperature effects on BTI and soft errors in modern logic circuits

Warin Sootkaneung, Sasithorn Chookaew, Suppachai Howimanporn, 2018, Microelectron. Reliab..

Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2012, 2012 25th International Conference on VLSI Design.

Soft error reduction through gate input dependent weighted sizing in combinational circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2011, 2011 12th International Symposium on Quality Electronic Design.

On techniques for handling soft errors in digital circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2010, 2010 IEEE International Test Conference.

Optimizing device size for soft error resilience in sub-micron logic circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Gate input reconfiguration for combating soft errors in combinational circuits

Kewal K. Saluja, Warin Sootkaneung, K. Saluja, 2010, 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W).

Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based Designs

Warin Sootkaneung, Sasithorn Chookaew, Suppachai Howimanporn, 2017, 2017 Euromicro Conference on Digital System Design (DSD).