B. Wuppermann

An 8.2 to 20.1 GHz LC PLL with Sub-100 fs Jitter in 0.13 µm SiGe BICMOS

J. Keane, M. Demirkan, G. Steinbach, 2010, 2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

Computer-generated holograms with error compensation.

W Freude, G K Grau, W Liebler, 1988, Applied optics.

A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS

A. Montijo, K. Poulton, R. Neff, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS

Ken Nishimura, Charles Wu, John P. Keane, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).