Paul M. Rosinger

发表

Power constrained test scheduling using power profile manipulation

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

Petru Eles, Bashir M. Al-Hashimi, Zebo Peng, 2008, J. Electron. Test..

Minimization of crosstalk noise, delay and power using a modified bus invert technique

Bashir M. Al-Hashimi, Paul M. Rosinger, Matheos Lampropoulos, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks

Luca Benini, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy

Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Alireza Ejlali, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Bridge Defect Diagnosis for Multiple-Voltage Design

Bashir M. Al-Hashimi, S. Saqib Khursheed, Sudhakar M. Reddy, 2008, 2008 13th European Test Symposium.

Scan architecture for shift and capture cycle power reduction

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

Petru Eles, Bashir M. Al-Hashimi, Zebo Peng, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Reducing Power Dissipation in SRAM during Test

Luigi Dilillo, Patrick Girard, Bashir M. Al-Hashimi, 2006, J. Low Power Electron..

Power profile manipulation: a new approach for reducing test application time under power constraints

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Bridging Fault Test Method With Adaptive Power Management Awareness

Bashir M. Al-Hashimi, S. Saqib Khursheed, Urban Ingelsson, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling

Krishnendu Chakrabarty, Bashir M. Al-Hashimi, Enkelejda Kasneci, 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC

Bashir M. Al-Hashimi, Rishad A. Shafik, Paul M. Rosinger, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks

Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Alireza Ejlali, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation

Bashir M. Al-Hashimi, Rishad A. Shafik, Paul M. Rosinger, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Minimizing Test Power in SRAM through Reduction of Pre-charge Activity

Luigi Dilillo, Bashir M. Al-Hashimi, Patrick Girard, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Rapid generation of thermal-safe test schedules

Krishnendu Chakrabarty, Bashir M. Al-Hashimi, Paul M. Rosinger, 2005, Design, Automation and Test in Europe.

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

Krishnendu Chakrabarty, Bashir M. Al-Hashimi, Paul M. Rosinger, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding

Bashir M. Al-Hashimi, Nicola Nicolici, Paul M. Rosinger, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems

Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Alireza Ejlali, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.