Akihisa Chikamura

Influence of lot arrival distribution on production dispatching rule scheduling and cost in the final test process of LSI manufacturing system

Koji Nakamae, Hiromu Fujioka, Akihisa Chikamura, 1998 .

Effect of 300 mm wafer and small lot size on final test process efficiency and cost of LSI manufacturing system

Koji Nakamae, Hiromu Fujioka, Akihisa Chikamura, 1998, IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168).

Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application

Koji Nakamae, Hiromu Fujioka, Akihisa Chikamura, 1999 .

TAT- and cost-reduction strategies in LSI manufacturing test process

Koji Nakamae, Hiromu Fujioka, Akihisa Chikamura, 1999, 10th Annual IEEE/SEMI. Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings (Cat. No.99CH36295).

Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process

Koji Nakamae, Hiromu Fujioka, Akihisa Chikamura, 1999 .

Effect of express lots on production dispatching rule scheduling and cost in final test process of LSI manufacturing system

Koji Nakamae, Hiromu Fujioka, Akihisa Chikamura, 1997, 1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023).

Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost

Koji Nakamae, Hiromu Fujioka, Akihisa Chikamura, 1999 .

EVALUATION OF PRODUCTION DISPATCHING RULES THROUGH SCHEDULING SIMULATION IN THE FINAL TEST PROCESS OF LSI MANUFACTURING SYSTEM

Koji Nakamae, Akihisa Chikamura, Hiromu Fujioka, 1996 .