Philip N. Strenski

Integrated analysis of power and performance for pipelined microprocessors

Michael Gschwind, David M. Brooks, Pradip Bose, 2004, IEEE Transactions on Computers.

Optimizing pipelines for power and performance

Michael Gschwind, David M. Brooks, Pradip Bose, 2002, MICRO.

Power–Performance Trade-Offs in Design of SoCs

Philip N. Strenski, Victor Zyuban, 2004 .

Optimizing pipelines for power and performance

Pradip Bose, Philip N. Strenski, Philip G. Emma, 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

U ncertai n ty-Aware Ci rcu i t Opt i m iziat ion

Philip N. Strenski, David J. Hathaway, Chandu Visweswariah, 2002 .

Analysis of finite length annealing schedules

Philip N. Strenski, Scott Kirkpatrick, 2005, Algorithmica.

Gradient-based optimization of custom circuits using a static-timing formulation

Philip N. Strenski, Andrew R. Conn, Chandramouli Visweswariah, 1999, DAC '99.

Balancing hardware intensity in microprocessor pipelines

Victor V. Zyuban, Philip N. Strenski, 2003, IBM J. Res. Dev..

Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels

Victor V. Zyuban, Philip N. Strenski, 2002, ISLPED '02.

Uncertainty-aware circuit optimization

Philip N. Strenski, Chandramouli Visweswariah, Xiaoliang Bai, 2002, DAC '02.